riscv_aplic.h File Reference

RISC-V APLIC (Advanced Platform-Level Interrupt Controller) driver API. More...

#include <zephyr/device.h>
#include <zephyr/types.h>

Go to the source code of this file.

Macros
APLIC Register Offsets
APLIC register offsets as defined in the AIA specification.
#define	APLIC_DOMAINCFG   0x0000
	Domain configuration register offset.
#define	APLIC_SOURCECFG_BASE   0x0004
	Source configuration registers base offset.
#define	APLIC_SETIP_BASE   0x1C00
	Set interrupt pending bitmap base offset.
#define	APLIC_SETIPNUM   0x1CDC
	Set interrupt pending by number register offset.
#define	APLIC_CLRIP_BASE   0x1D00
	Clear interrupt pending bitmap base offset.
#define	APLIC_CLRIPNUM   0x1DDC
	Clear interrupt pending by number register offset.
#define	APLIC_SETIE_BASE   0x1E00
	Set interrupt enable bitmap base offset.
#define	APLIC_SETIENUM   0x1EDC
	Set interrupt enable by number register offset.
#define	APLIC_CLRIE_BASE   0x1F00
	Clear interrupt enable bitmap base offset.
#define	APLIC_CLRIENUM   0x1FDC
	Clear interrupt enable by number register offset.
#define	APLIC_MSIADDRCFG   0x1BC0
	MSI address configuration register offset.
#define	APLIC_MSIADDRCFGH   0x1BC4
	MSI address configuration high register offset.
#define	APLIC_SMSIADDRCFG   0x1BC8
	Supervisor MSI address configuration register offset.
#define	APLIC_SMSIADDRCFGH   0x1BCC
	Supervisor MSI address configuration high register offset.
#define	APLIC_GENMSI   0x3000
	Generate MSI register offset.
#define	APLIC_TARGET_BASE   0x3004
	Target registers base offset.
APLIC Domain Configuration Bits
Bit definitions for the APLIC domain configuration register.
#define	APLIC_DOMAINCFG_IE   BIT(8)
	Interrupt enable bit in domaincfg.
#define	APLIC_DOMAINCFG_DM   BIT(2)
	Delivery mode bit in domaincfg (1=MSI mode).
#define	APLIC_DOMAINCFG_BE   BIT(0)
	Big endian bit in domaincfg.
APLIC MSI Address Configuration Fields
Bit field definitions for MSIADDRCFGH register used by APLIC to calculate per-hart MSI target addresses.
#define	APLIC_MSIADDRCFGH_L_BIT   31
	Lock bit position in MSIADDRCFGH.
#define	APLIC_MSIADDRCFGH_HHXS_SHIFT   24
	Higher Hart Index Shift field position.
#define	APLIC_MSIADDRCFGH_HHXS_MASK   0x1F
	Higher Hart Index Shift field mask.
#define	APLIC_MSIADDRCFGH_LHXS_SHIFT   20
	Lower Hart Index Shift field position.
#define	APLIC_MSIADDRCFGH_LHXS_MASK   0x7
	Lower Hart Index Shift field mask.
#define	APLIC_MSIADDRCFGH_HHXW_SHIFT   16
	Higher Hart Index Width field position.
#define	APLIC_MSIADDRCFGH_HHXW_MASK   0x7
	Higher Hart Index Width field mask.
#define	APLIC_MSIADDRCFGH_LHXW_SHIFT   12
	Lower Hart Index Width field position.
#define	APLIC_MSIADDRCFGH_LHXW_MASK   0xF
	Lower Hart Index Width field mask.
#define	APLIC_MSIADDRCFGH_BAPPN_MASK   0xFFF
	Base address PPN field mask (upper address bits).
APLIC Source Configuration Fields
Bit field definitions for source configuration registers.
#define	APLIC_SOURCECFG_D_BIT   10
	Delegate bit position in sourcecfg.
#define	APLIC_SOURCECFG_SM_MASK   0x7
	Source mode field mask (bits 2:0).
#define	APLIC_SM_INACTIVE   0x0
	Source mode: inactive.
#define	APLIC_SM_DETACHED   0x1
	Source mode: detached (delegated to child domain).
#define	APLIC_SM_EDGE_RISE   0x4
	Source mode: rising edge triggered.
#define	APLIC_SM_EDGE_FALL   0x5
	Source mode: falling edge triggered.
#define	APLIC_SM_LEVEL_HIGH   0x6
	Source mode: active high level triggered.
#define	APLIC_SM_LEVEL_LOW   0x7
	Source mode: active low level triggered.
APLIC Target Register Fields
Bit field definitions for TARGET registers (MSI routing).
#define	APLIC_TARGET_HART_SHIFT   18
	Hart index field shift in TARGET register.
#define	APLIC_TARGET_HART_MASK   0x3FFF
	Hart index field mask (14-bit, bits 31:18).
#define	APLIC_TARGET_MSI_DEL   BIT(11)
	MSI delivery mode bit (0=DMSI, 1=MMSI).
#define	APLIC_TARGET_EIID_MASK   0x7FF
	External Interrupt Identity field mask (11-bit, bits 10:0).
APLIC GENMSI Register Fields
Bit field definitions for software-triggered MSI generation.
#define	APLIC_GENMSI_HART_SHIFT   18
	Hart index field shift in GENMSI register.
#define	APLIC_GENMSI_HART_MASK   0x3FFF
	Hart index field mask (14-bit, bits 31:18).
#define	APLIC_GENMSI_CONTEXT_SHIFT   13
	Context/Guest field shift (bits 17:13).
#define	APLIC_GENMSI_CONTEXT_MASK   0x1F
	Context field mask (5-bit, for DMSI).
#define	APLIC_GENMSI_BUSY   BIT(12)
	Busy bit (read-only status).
#define	APLIC_GENMSI_MMSI_MODE   BIT(11)
	MSI delivery mode (0=DMSI, 1=MMSI).
#define	APLIC_GENMSI_EIID_MASK   0x7FF
	External Interrupt Identity field mask (11-bit, bits 10:0).

Functions
static uint32_t	aplic_sourcecfg_off (unsigned int src)
	Calculate sourcecfg register offset for a source.
static uint32_t	aplic_target_off (unsigned int src)
	Calculate target register offset for a source.
static const struct device *	riscv_aplic_get_dev (void)
	Get the APLIC device instance.
int	riscv_aplic_domain_enable (const struct device *dev, bool enable)
	Enable or disable the APLIC domain.
int	riscv_aplic_config_src (const struct device *dev, unsigned int src, unsigned int sm)
	Configure an interrupt source mode.
int	riscv_aplic_enable_src (const struct device *dev, unsigned int src, bool enable)
	Enable or disable an interrupt source.
int	riscv_aplic_msi_route (const struct device *dev, unsigned int src, uint32_t hart, uint32_t eiid)
	Configure MSI routing for an interrupt source.
int	riscv_aplic_msi_inject_software_interrupt (const struct device *dev, uint32_t eiid, uint32_t hart_id, uint32_t context)
	Inject a software-triggered MSI.
uint32_t	riscv_aplic_get_num_sources (const struct device *dev)
	Get the number of interrupt sources.
static void	riscv_aplic_enable_source (unsigned int src)
	Enable an interrupt source (convenience wrapper).
static void	riscv_aplic_disable_source (unsigned int src)
	Disable an interrupt source (convenience wrapper).
static void	riscv_aplic_msi_inject_genmsi (uint32_t hart, uint32_t eiid)
	Inject MSI using GENMSI (convenience wrapper).

Detailed Description

RISC-V APLIC (Advanced Platform-Level Interrupt Controller) driver API.

This header provides the API and register definitions for the RISC-V Advanced Platform-Level Interrupt Controller (APLIC). The APLIC is part of the RISC-V Advanced Interrupt Architecture (AIA) and supports both MSI and direct delivery modes.

Macro Definition Documentation

APLIC_CLRIE_BASE

#define APLIC_CLRIE_BASE   0x1F00

Clear interrupt enable bitmap base offset.

APLIC_CLRIENUM

#define APLIC_CLRIENUM   0x1FDC

Clear interrupt enable by number register offset.

APLIC_CLRIP_BASE

#define APLIC_CLRIP_BASE   0x1D00

Clear interrupt pending bitmap base offset.

APLIC_CLRIPNUM

#define APLIC_CLRIPNUM   0x1DDC

Clear interrupt pending by number register offset.

APLIC_DOMAINCFG

#define APLIC_DOMAINCFG   0x0000

Domain configuration register offset.

APLIC_DOMAINCFG_BE

#define APLIC_DOMAINCFG_BE   BIT(0)

Big endian bit in domaincfg.

APLIC_DOMAINCFG_DM

#define APLIC_DOMAINCFG_DM   BIT(2)

Delivery mode bit in domaincfg (1=MSI mode).

APLIC_DOMAINCFG_IE

#define APLIC_DOMAINCFG_IE   BIT(8)

Interrupt enable bit in domaincfg.

APLIC_GENMSI

#define APLIC_GENMSI   0x3000

Generate MSI register offset.

APLIC_GENMSI_BUSY

#define APLIC_GENMSI_BUSY   BIT(12)

Busy bit (read-only status).

APLIC_GENMSI_CONTEXT_MASK

#define APLIC_GENMSI_CONTEXT_MASK   0x1F

Context field mask (5-bit, for DMSI).

APLIC_GENMSI_CONTEXT_SHIFT

#define APLIC_GENMSI_CONTEXT_SHIFT   13

Context/Guest field shift (bits 17:13).

APLIC_GENMSI_EIID_MASK

#define APLIC_GENMSI_EIID_MASK   0x7FF

External Interrupt Identity field mask (11-bit, bits 10:0).

APLIC_GENMSI_HART_MASK

#define APLIC_GENMSI_HART_MASK   0x3FFF

Hart index field mask (14-bit, bits 31:18).

APLIC_GENMSI_HART_SHIFT

#define APLIC_GENMSI_HART_SHIFT   18

Hart index field shift in GENMSI register.

APLIC_GENMSI_MMSI_MODE

#define APLIC_GENMSI_MMSI_MODE   BIT(11)

MSI delivery mode (0=DMSI, 1=MMSI).

APLIC_MSIADDRCFG

#define APLIC_MSIADDRCFG   0x1BC0

MSI address configuration register offset.

APLIC_MSIADDRCFGH

#define APLIC_MSIADDRCFGH   0x1BC4

MSI address configuration high register offset.

APLIC_MSIADDRCFGH_BAPPN_MASK

#define APLIC_MSIADDRCFGH_BAPPN_MASK   0xFFF

Base address PPN field mask (upper address bits).

APLIC_MSIADDRCFGH_HHXS_MASK

#define APLIC_MSIADDRCFGH_HHXS_MASK   0x1F

Higher Hart Index Shift field mask.

APLIC_MSIADDRCFGH_HHXS_SHIFT

#define APLIC_MSIADDRCFGH_HHXS_SHIFT   24

Higher Hart Index Shift field position.

APLIC_MSIADDRCFGH_HHXW_MASK

#define APLIC_MSIADDRCFGH_HHXW_MASK   0x7

Higher Hart Index Width field mask.

APLIC_MSIADDRCFGH_HHXW_SHIFT

#define APLIC_MSIADDRCFGH_HHXW_SHIFT   16

Higher Hart Index Width field position.

APLIC_MSIADDRCFGH_L_BIT

#define APLIC_MSIADDRCFGH_L_BIT   31

Lock bit position in MSIADDRCFGH.

APLIC_MSIADDRCFGH_LHXS_MASK

#define APLIC_MSIADDRCFGH_LHXS_MASK   0x7

Lower Hart Index Shift field mask.

APLIC_MSIADDRCFGH_LHXS_SHIFT

#define APLIC_MSIADDRCFGH_LHXS_SHIFT   20

Lower Hart Index Shift field position.

APLIC_MSIADDRCFGH_LHXW_MASK

#define APLIC_MSIADDRCFGH_LHXW_MASK   0xF

Lower Hart Index Width field mask.

APLIC_MSIADDRCFGH_LHXW_SHIFT

#define APLIC_MSIADDRCFGH_LHXW_SHIFT   12

Lower Hart Index Width field position.

APLIC_SETIE_BASE

#define APLIC_SETIE_BASE   0x1E00

Set interrupt enable bitmap base offset.

APLIC_SETIENUM

#define APLIC_SETIENUM   0x1EDC

Set interrupt enable by number register offset.

APLIC_SETIP_BASE

#define APLIC_SETIP_BASE   0x1C00

Set interrupt pending bitmap base offset.

APLIC_SETIPNUM

#define APLIC_SETIPNUM   0x1CDC

Set interrupt pending by number register offset.

APLIC_SM_DETACHED

#define APLIC_SM_DETACHED   0x1

Source mode: detached (delegated to child domain).

APLIC_SM_EDGE_FALL

#define APLIC_SM_EDGE_FALL   0x5

Source mode: falling edge triggered.

APLIC_SM_EDGE_RISE

#define APLIC_SM_EDGE_RISE   0x4

Source mode: rising edge triggered.

APLIC_SM_INACTIVE

#define APLIC_SM_INACTIVE   0x0

Source mode: inactive.

APLIC_SM_LEVEL_HIGH

#define APLIC_SM_LEVEL_HIGH   0x6

Source mode: active high level triggered.

APLIC_SM_LEVEL_LOW

#define APLIC_SM_LEVEL_LOW   0x7

Source mode: active low level triggered.

APLIC_SMSIADDRCFG

#define APLIC_SMSIADDRCFG   0x1BC8

Supervisor MSI address configuration register offset.

APLIC_SMSIADDRCFGH

#define APLIC_SMSIADDRCFGH   0x1BCC

Supervisor MSI address configuration high register offset.

APLIC_SOURCECFG_BASE

#define APLIC_SOURCECFG_BASE   0x0004

Source configuration registers base offset.

APLIC_SOURCECFG_D_BIT

#define APLIC_SOURCECFG_D_BIT   10

Delegate bit position in sourcecfg.

APLIC_SOURCECFG_SM_MASK

#define APLIC_SOURCECFG_SM_MASK   0x7

Source mode field mask (bits 2:0).

APLIC_TARGET_BASE

#define APLIC_TARGET_BASE   0x3004

Target registers base offset.

APLIC_TARGET_EIID_MASK

#define APLIC_TARGET_EIID_MASK   0x7FF

External Interrupt Identity field mask (11-bit, bits 10:0).

APLIC_TARGET_HART_MASK

#define APLIC_TARGET_HART_MASK   0x3FFF

Hart index field mask (14-bit, bits 31:18).

APLIC_TARGET_HART_SHIFT

#define APLIC_TARGET_HART_SHIFT   18

Hart index field shift in TARGET register.

APLIC_TARGET_MSI_DEL

#define APLIC_TARGET_MSI_DEL   BIT(11)

MSI delivery mode bit (0=DMSI, 1=MMSI).

Function Documentation

aplic_sourcecfg_off()

uint32_t aplic_sourcecfg_off ( unsigned int src )

inlinestatic

Calculate sourcecfg register offset for a source.

Parameters

src	Interrupt source number (1-based)

Returns

Register offset for the source's configuration register

aplic_target_off()

uint32_t aplic_target_off ( unsigned int src )

inlinestatic

Calculate target register offset for a source.

Parameters

src	Interrupt source number (1-based)

Returns

Register offset for the source's target register

riscv_aplic_config_src()

int riscv_aplic_config_src	(	const struct device *	dev,
		unsigned int	src,
		unsigned int	sm )

Configure an interrupt source mode.

Sets the trigger mode for an interrupt source (edge/level, polarity).

Parameters

dev	APLIC device
src	Interrupt source number
sm	Source mode (APLIC_SM_* values)

Returns

0 on success, negative error code on failure

riscv_aplic_disable_source()

void riscv_aplic_disable_source ( unsigned int src )

inlinestatic

Disable an interrupt source (convenience wrapper).

Disables the specified interrupt source using the default APLIC device.

Parameters

src	Interrupt source number

riscv_aplic_domain_enable()

int riscv_aplic_domain_enable	(	const struct device *	dev,
		bool	enable )

Enable or disable the APLIC domain.

Controls the interrupt enable bit in the domain configuration register.

Parameters

dev	APLIC device
enable	true to enable the domain, false to disable

Returns

0 on success, negative error code on failure

riscv_aplic_enable_source()

void riscv_aplic_enable_source ( unsigned int src )

inlinestatic

Enable an interrupt source (convenience wrapper).

Enables the specified interrupt source using the default APLIC device.

Parameters

src	Interrupt source number

riscv_aplic_enable_src()

int riscv_aplic_enable_src	(	const struct device *	dev,
		unsigned int	src,
		bool	enable )

Enable or disable an interrupt source.

Controls whether the specified interrupt source can generate interrupts.

Parameters

dev	APLIC device
src	Interrupt source number
enable	true to enable, false to disable

Returns

0 on success, negative error code on failure

riscv_aplic_get_dev()

const struct device * riscv_aplic_get_dev ( void )

inlinestatic

Get the APLIC device instance.

Returns the device structure for the APLIC driver.

Returns

Pointer to the APLIC device

riscv_aplic_get_num_sources()

uint32_t riscv_aplic_get_num_sources

(

const struct device *

dev

)

Get the number of interrupt sources.

Returns the number of interrupt sources supported by the APLIC.

Parameters

dev	APLIC device

Returns

Number of interrupt sources

riscv_aplic_msi_inject_genmsi()

void riscv_aplic_msi_inject_genmsi ( uint32_t hart, uint32_t eiid )

inlinestatic

Inject MSI using GENMSI (convenience wrapper).

Injects a software MSI to the specified hart using the default APLIC device.

Parameters

hart	Target hart index
eiid	External Interrupt Identity

riscv_aplic_msi_inject_software_interrupt()

int riscv_aplic_msi_inject_software_interrupt	(	const struct device *	dev,
		uint32_t	eiid,
		uint32_t	hart_id,
		uint32_t	context )

Inject a software-triggered MSI.

Triggers an MSI to the specified hart using the GENMSI register.

Parameters

dev	APLIC device
eiid	External Interrupt Identity
hart_id	Target hart index
context	Context field (for DMSI mode)

Returns

0 on success, negative error code on failure

riscv_aplic_msi_route()

int riscv_aplic_msi_route	(	const struct device *	dev,
		unsigned int	src,
		uint32_t	hart,
		uint32_t	eiid )

Configure MSI routing for an interrupt source.

Sets the target hart and EIID for MSI delivery of the specified source.

Parameters

dev	APLIC device
src	Interrupt source number
hart	Target hart index
eiid	External Interrupt Identity for the target IMSIC

Returns

0 on success, negative error code on failure