|
| #define | DMA_REQSEL_NONE (FIELD_PREP(DMA_SRC_MASK, 0) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_LDMAXBAR0PRSREQ0 (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_LDMAXBAR0PRSREQ1 (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_TIMER0CC0 (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_TIMER0CC1 (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_TIMER0CC2 (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 2)) |
| #define | DMA_REQSEL_TIMER0UFOF (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 3)) |
| #define | DMA_REQSEL_TIMER1CC0 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_TIMER1CC1 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_TIMER1CC2 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 2)) |
| #define | DMA_REQSEL_TIMER1UFOF (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 3)) |
| #define | DMA_REQSEL_I2C0RXDATAV (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_I2C0TXBL (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_I2C1RXDATAV (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_I2C1TXBL (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_TIMER2CC0 (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_TIMER2CC1 (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_TIMER2CC2 (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 2)) |
| #define | DMA_REQSEL_TIMER2UFOF (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 3)) |
| #define | DMA_REQSEL_TIMER2CC3 (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 4)) |
| #define | DMA_REQSEL_TIMER2CC4 (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 5)) |
| #define | DMA_REQSEL_TIMER2CC5 (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 6)) |
| #define | DMA_REQSEL_TIMER2CC6 (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 7)) |
| #define | DMA_REQSEL_TIMER3CC0 (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_TIMER3CC1 (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_TIMER3CC2 (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 2)) |
| #define | DMA_REQSEL_TIMER3UFOF (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 3)) |
| #define | DMA_REQSEL_TIMER3CC3 (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 4)) |
| #define | DMA_REQSEL_TIMER3CC4 (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 5)) |
| #define | DMA_REQSEL_TIMER3CC5 (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 6)) |
| #define | DMA_REQSEL_TIMER3CC6 (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 7)) |
| #define | DMA_REQSEL_EUSART1RXFL (FIELD_PREP(DMA_SRC_MASK, 8) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_EUSART1TXFL (FIELD_PREP(DMA_SRC_MASK, 8) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_EUSART0RXFL (FIELD_PREP(DMA_SRC_MASK, 9) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_EUSART0TXFL (FIELD_PREP(DMA_SRC_MASK, 9) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_ADC0SCAN (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_PIXELRZ0REQ_TXF (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_EUSART2RXFL (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_EUSART2TXFL (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 1)) |
| #define | DMA_REQSEL_PIXELRZ1REQ_TXF (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_I2C2RXDATAV (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 0)) |
| #define | DMA_REQSEL_I2C2TXBL (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 1)) |