Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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stm32-fmc-sdram.h File Reference

Go to the source code of this file.

Macros

#define STM32_FMC_SDRAM_NC_8   0x00000000UL
 
#define STM32_FMC_SDRAM_NC_9   0x00000001UL
 
#define STM32_FMC_SDRAM_NC_10   0x00000002UL
 
#define STM32_FMC_SDRAM_NC_11   0x00000003UL
 
#define STM32_FMC_SDRAM_NR_11   0x00000000UL
 
#define STM32_FMC_SDRAM_NR_12   0x00000004UL
 
#define STM32_FMC_SDRAM_NR_13   0x00000008UL
 
#define STM32_FMC_SDRAM_MWID_8   0x00000000UL
 
#define STM32_FMC_SDRAM_MWID_16   0x00000010UL
 
#define STM32_FMC_SDRAM_MWID_32   0x00000020UL
 
#define STM32_FMC_SDRAM_NB_2   0x00000000UL
 
#define STM32_FMC_SDRAM_NB_4   0x00000040UL
 
#define STM32_FMC_SDRAM_CAS_1   0x00000080UL
 
#define STM32_FMC_SDRAM_CAS_2   0x00000100UL
 
#define STM32_FMC_SDRAM_CAS_3   0x00000180UL
 
#define STM32_FMC_SDRAM_SDCLK_DISABLE   0x00000000UL
 
#define STM32_FMC_SDRAM_SDCLK_PERIOD_2   0x00000800UL
 
#define STM32_FMC_SDRAM_SDCLK_PERIOD_3   0x00000C00UL
 
#define STM32_FMC_SDRAM_RBURST_DISABLE   0x00000000UL
 
#define STM32_FMC_SDRAM_RBURST_ENABLE   0x00001000UL
 
#define STM32_FMC_SDRAM_RPIPE_0   0x00000000UL
 
#define STM32_FMC_SDRAM_RPIPE_1   0x00002000UL
 
#define STM32_FMC_SDRAM_RPIPE_2   0x00004000UL
 

Macro Definition Documentation

◆ STM32_FMC_SDRAM_CAS_1

#define STM32_FMC_SDRAM_CAS_1   0x00000080UL

◆ STM32_FMC_SDRAM_CAS_2

#define STM32_FMC_SDRAM_CAS_2   0x00000100UL

◆ STM32_FMC_SDRAM_CAS_3

#define STM32_FMC_SDRAM_CAS_3   0x00000180UL

◆ STM32_FMC_SDRAM_MWID_16

#define STM32_FMC_SDRAM_MWID_16   0x00000010UL

◆ STM32_FMC_SDRAM_MWID_32

#define STM32_FMC_SDRAM_MWID_32   0x00000020UL

◆ STM32_FMC_SDRAM_MWID_8

#define STM32_FMC_SDRAM_MWID_8   0x00000000UL

◆ STM32_FMC_SDRAM_NB_2

#define STM32_FMC_SDRAM_NB_2   0x00000000UL

◆ STM32_FMC_SDRAM_NB_4

#define STM32_FMC_SDRAM_NB_4   0x00000040UL

◆ STM32_FMC_SDRAM_NC_10

#define STM32_FMC_SDRAM_NC_10   0x00000002UL

◆ STM32_FMC_SDRAM_NC_11

#define STM32_FMC_SDRAM_NC_11   0x00000003UL

◆ STM32_FMC_SDRAM_NC_8

#define STM32_FMC_SDRAM_NC_8   0x00000000UL

◆ STM32_FMC_SDRAM_NC_9

#define STM32_FMC_SDRAM_NC_9   0x00000001UL

◆ STM32_FMC_SDRAM_NR_11

#define STM32_FMC_SDRAM_NR_11   0x00000000UL

◆ STM32_FMC_SDRAM_NR_12

#define STM32_FMC_SDRAM_NR_12   0x00000004UL

◆ STM32_FMC_SDRAM_NR_13

#define STM32_FMC_SDRAM_NR_13   0x00000008UL

◆ STM32_FMC_SDRAM_RBURST_DISABLE

#define STM32_FMC_SDRAM_RBURST_DISABLE   0x00000000UL

◆ STM32_FMC_SDRAM_RBURST_ENABLE

#define STM32_FMC_SDRAM_RBURST_ENABLE   0x00001000UL

◆ STM32_FMC_SDRAM_RPIPE_0

#define STM32_FMC_SDRAM_RPIPE_0   0x00000000UL

◆ STM32_FMC_SDRAM_RPIPE_1

#define STM32_FMC_SDRAM_RPIPE_1   0x00002000UL

◆ STM32_FMC_SDRAM_RPIPE_2

#define STM32_FMC_SDRAM_RPIPE_2   0x00004000UL

◆ STM32_FMC_SDRAM_SDCLK_DISABLE

#define STM32_FMC_SDRAM_SDCLK_DISABLE   0x00000000UL

◆ STM32_FMC_SDRAM_SDCLK_PERIOD_2

#define STM32_FMC_SDRAM_SDCLK_PERIOD_2   0x00000800UL

◆ STM32_FMC_SDRAM_SDCLK_PERIOD_3

#define STM32_FMC_SDRAM_SDCLK_PERIOD_3   0x00000C00UL