Zephyr Project API 4.4.99
A Scalable Open Source RTOS
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stm32_common_clocks.h File Reference

Go to the source code of this file.

Macros

#define STM32_SRC_SYSCLK   0x001
 ID for system clock as source clock.
#define STM32_SRC_LSE   0x002
 ID for LSE clock as source clock.
#define STM32_SRC_LSI   0x003
 ID for LSI clock as source clock.
#define NO_SEL   0xFF
 Dummy: Add a specifier when no selection is possible.
#define STM32_CLOCK_DIV(div)
 Clock divider.
#define STM32_DT_CLOCK_SELECT(val, msb, lsb, reg)
 Pack STM32 source clock selection RCC register bit fields for the DT.
#define STM32_CLOCK(bus, bit)
 Pack RCC clock register offset and bit in two 32-bit values as expected for the Device Tree clocks property on STM32.

Macro Definition Documentation

◆ NO_SEL

#define NO_SEL   0xFF

Dummy: Add a specifier when no selection is possible.

◆ STM32_CLOCK

#define STM32_CLOCK ( bus,
bit )
Value:
(STM32_CLOCK_BUS_##bus) (1 << bit)

Pack RCC clock register offset and bit in two 32-bit values as expected for the Device Tree clocks property on STM32.

Parameters
busSTM32 bus name (expands to STM32_CLOCK_BUS_{bus})
bitClock bit

◆ STM32_CLOCK_DIV

#define STM32_CLOCK_DIV ( div)
Value:
(((div) - 1) << STM32_CLOCK_DIV_SHIFT)
#define STM32_CLOCK_DIV_SHIFT
Definition stm32_clock.h:27

Clock divider.

◆ STM32_DT_CLOCK_SELECT

#define STM32_DT_CLOCK_SELECT ( val,
msb,
lsb,
reg )
Value:
((((reg) & STM32_DT_CLKSEL_REG_MASK) << STM32_DT_CLKSEL_REG_SHIFT) | \
(((lsb) & STM32_DT_CLKSEL_SHIFT_MASK) << STM32_DT_CLKSEL_SHIFT_SHIFT) | \
((((msb) - (lsb)) & STM32_DT_CLKSEL_WIDTH_MASK) << STM32_DT_CLKSEL_WIDTH_SHIFT) | \
(((val) & STM32_DT_CLKSEL_VAL_MASK) << STM32_DT_CLKSEL_VAL_SHIFT))

Pack STM32 source clock selection RCC register bit fields for the DT.

Parameters
valClock configuration field value
msbField MSB's index
lsbField LSB's index
regOffset to target clock configuration register in RCC
Note
Internally, the data are stored as follows
'reg' range: 0x0~0xFFFF [ 00 : 15 ]
'shift' range: 0~31 [ 16 : 20 ]
'width' range: 0~7 [ 21 : 23 ] Value encodes bit fields width minus 1
'val' range: 0x00~0xFF [ 24 : 31 ]

◆ STM32_SRC_LSE

#define STM32_SRC_LSE   0x002

ID for LSE clock as source clock.

◆ STM32_SRC_LSI

#define STM32_SRC_LSI   0x003

ID for LSI clock as source clock.

◆ STM32_SRC_SYSCLK

#define STM32_SRC_SYSCLK   0x001

ID for system clock as source clock.