Zephyr Project API
4.4.99
A Scalable Open Source RTOS
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stm32c5_clock.h
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/*
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* Copyright (c) 2026 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C5_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C5_CLOCK_H_
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#include <
zephyr/dt-bindings/clock/stm32_common_clocks.h
>
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/* RM0522, Figure 24 Clock tree for STM32C5 Series */
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/* defined in stm32_common_clocks.h */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSIS (STM32_SRC_HSE + 1)
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#define STM32_SRC_HSIDIV3 (STM32_SRC_HSIS + 1)
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#define STM32_SRC_HSIK (STM32_SRC_HSIDIV3 + 1)
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#define STM32_SRC_PSIS (STM32_SRC_HSIK + 1)
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#define STM32_SRC_PSIDIV3 (STM32_SRC_PSIS + 1)
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#define STM32_SRC_PSIK (STM32_SRC_PSIDIV3 + 1)
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#define STM32_SRC_HCLK (STM32_SRC_PSIK + 1)
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#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
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#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
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#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
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/* Clock muxes */
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#define STM32_SRC_CK48 (STM32_SRC_PCLK3 + 1)
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/* #define STM32_SRC_AUDIOCLK TBD */
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#define STM32_CLOCK_BUS_AHB1 0x088
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#define STM32_CLOCK_BUS_AHB2 0x08C
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#define STM32_CLOCK_BUS_AHB4 0x094
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#define STM32_CLOCK_BUS_APB1 0x09C
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#define STM32_CLOCK_BUS_APB1_2 0x0A0
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#define STM32_CLOCK_BUS_APB2 0x0A4
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#define STM32_CLOCK_BUS_APB3 0x0A8
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
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#define CCIPR1_REG 0xD8
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#define CCIPR2_REG 0xDC
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#define CCIPR3_REG 0xE0
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#define RTCCR_REG 0xF0
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#define CFGR1_REG 0x1C
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#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR1_REG)
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#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG)
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#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, CCIPR1_REG)
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#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR1_REG)
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#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR1_REG)
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#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR1_REG)
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#define UART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR1_REG)
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#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 14, CCIPR1_REG)
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#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR1_REG)
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#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR1_REG)
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#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR1_REG)
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#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR1_REG)
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#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG)
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#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG)
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#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR2_REG)
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#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR2_REG)
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#define ADCDACPRE_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR2_REG)
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#define DAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 15, CCIPR2_REG)
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#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR2_REG)
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#define CK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 24, CCIPR2_REG)
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#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, CCIPR2_REG)
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#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR3_REG)
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#define ETH1REFCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 8, CCIPR3_REG)
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#define ETH1PTPCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR3_REG)
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#define ETH1CLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 13, CCIPR3_REG)
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#define ETH1CLKDIV_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR3_REG)
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#define ETH1PTPDIV_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 28, CCIPR3_REG)
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, RTCCR_REG)
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#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 21, 18, CFGR1_REG)
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 22, CFGR1_REG)
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#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 28, 25, CFGR1_REG)
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#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CFGR1_REG)
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#define MCO_PRE_DIV_1 1
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#define MCO_PRE_DIV_2 2
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#define MCO_PRE_DIV_3 3
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#define MCO_PRE_DIV_4 4
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#define MCO_PRE_DIV_5 5
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#define MCO_PRE_DIV_6 6
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#define MCO_PRE_DIV_7 7
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#define MCO_PRE_DIV_8 8
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#define MCO_PRE_DIV_9 9
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#define MCO_PRE_DIV_10 10
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#define MCO_PRE_DIV_11 11
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#define MCO_PRE_DIV_12 12
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#define MCO_PRE_DIV_13 13
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#define MCO_PRE_DIV_14 14
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#define MCO_PRE_DIV_15 15
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#define MCO1_SEL_SYSCLK 0
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#define MCO1_SEL_HSE 1
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#define MCO1_SEL_LSE 2
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#define MCO1_SEL_LSI 3
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#define MCO1_SEL_PSIK 4
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#define MCO1_SEL_HSIK 5
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#define MCO1_SEL_PSIS 6
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#define MCO1_SEL_HSIS 7
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#define MCO2_SEL_SYSCLK 0
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#define MCO2_SEL_HSE 1
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#define MCO2_SEL_LSE 2
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#define MCO2_SEL_LSI 3
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#define MCO2_SEL_PSIK 4
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#define MCO2_SEL_HSIK 5
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#define MCO2_SEL_PSIDIV3 6
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#define MCO2_SEL_HSIDIV3 7
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C5_CLOCK_H_ */
stm32_common_clocks.h
include
zephyr
dt-bindings
clock
stm32c5_clock.h
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