Zephyr Project API
3.7.0
A Scalable Open Source RTOS
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stm32f410_clock.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2023 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
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#define DCKCFGR_REG 0x8C
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#define DCKCFGR2_REG 0x94
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#define CKDFSDM2A_SEL(val) STM32_CLOCK(val, 1, 14, DCKCFGR_REG)
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#define CKDFSDM1A_SEL(val) STM32_CLOCK(val, 1, 15, DCKCFGR_REG)
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#define SAI1A_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR_REG)
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#define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG)
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#define I2S1_SEL(val) STM32_CLOCK(val, 3, 25, DCKCFGR_REG)
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#define I2S2_SEL(val) STM32_CLOCK(val, 3, 27, DCKCFGR_REG)
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#define CKDFSDM_SEL(val) STM32_CLOCK(val, 1, 31, DCKCFGR_REG)
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#define I2CFMP1_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG)
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#define CK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR2_REG)
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#define SDIO_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR2_REG)
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#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 30, DCKCFGR2_REG)
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/* F4 generic I2S_SEL is not compatible with F410 devices */
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#ifdef I2S_SEL
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#undef I2S_SEL
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#endif
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ */
include
zephyr
dt-bindings
clock
stm32f410_clock.h
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