stm32f4_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_CLOCK_BUS_AHB1   0x030
	Domain clocks.
#define	STM32_CLOCK_BUS_AHB2   0x034
#define	STM32_CLOCK_BUS_AHB3   0x038
#define	STM32_CLOCK_BUS_APB1   0x040
#define	STM32_CLOCK_BUS_APB2   0x044
#define	STM32_CLOCK_BUS_APB3   0x0A8
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3
#define	STM32_SRC_HSI   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_HSE   (STM32_SRC_HSI + 1)
#define	STM32_SRC_PLL_P   (STM32_SRC_HSE + 1)
	PLL clock outputs.
#define	STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)
#define	STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)
#define	STM32_SRC_PLLI2S_Q   (STM32_SRC_PLL_R + 1)
	I2S sources.
#define	STM32_SRC_PLLI2S_R   (STM32_SRC_PLLI2S_Q + 1)
#define	STM32_SRC_CK48   (STM32_SRC_PLLI2S_R + 1)
#define	CFGR_REG   0x08
	RCC_CFGRx register offset.
#define	BDCR_REG   0x70
	RCC_BDCR register offset.
#define	I2S_SEL(val)   STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG)
	Device domain clocks selection helpers.
#define	MCO1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG)
#define	MCO1_PRE(val)   STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG)
#define	MCO2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG)
#define	MCO2_PRE(val)   STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG)
#define	RTC_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
	BDCR devices.
#define	MCO_PRE_DIV_1   0
#define	MCO_PRE_DIV_2   4
#define	MCO_PRE_DIV_3   5
#define	MCO_PRE_DIV_4   6
#define	MCO_PRE_DIV_5   7

Macro Definition Documentation

BDCR_REG

#define BDCR_REG   0x70

RCC_BDCR register offset.

CFGR_REG

#define CFGR_REG   0x08

RCC_CFGRx register offset.

I2S_SEL

#define I2S_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG)

Device domain clocks selection helpers.

CFGR devices

MCO1_PRE

#define MCO1_PRE

(

val

)

STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG)

MCO2_PRE

#define MCO2_PRE

(

val

)

STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG)

MCO2_SEL

#define MCO2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG)

MCO_PRE_DIV_1

#define MCO_PRE_DIV_1   0

MCO_PRE_DIV_2

#define MCO_PRE_DIV_2   4

MCO_PRE_DIV_3

#define MCO_PRE_DIV_3   5

MCO_PRE_DIV_4

#define MCO_PRE_DIV_4   6

MCO_PRE_DIV_5

#define MCO_PRE_DIV_5   7

RTC_SEL

#define RTC_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)

BDCR devices.

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x030

Domain clocks.

Bus clocks

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x034

STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x038

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x040

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x044

STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x0A8

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_CK48

#define STM32_SRC_CK48   (STM32_SRC_PLLI2S_R + 1)

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_HSI + 1)

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_PLL_P

#define STM32_SRC_PLL_P   (STM32_SRC_HSE + 1)

PLL clock outputs.

STM32_SRC_PLL_Q

#define STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)

STM32_SRC_PLL_R

#define STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)

STM32_SRC_PLLI2S_Q

#define STM32_SRC_PLLI2S_Q   (STM32_SRC_PLL_R + 1)

I2S sources.

STM32_SRC_PLLI2S_R

#define STM32_SRC_PLLI2S_R   (STM32_SRC_PLLI2S_Q + 1)