Go to the source code of this file.
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#define | STM32_CLOCK_BUS_AHB1 0x014 |
| Bus gatting clocks.
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#define | STM32_CLOCK_BUS_APB2 0x018 |
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#define | STM32_CLOCK_BUS_APB1 0x01c |
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#define | STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 |
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#define | STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 |
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#define | STM32_SRC_HSI (STM32_SRC_LSI + 1) |
| Domain clocks.
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#define | STM32_SRC_HSI14 (STM32_SRC_HSI + 1) |
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#define | STM32_SRC_HSI48 (STM32_SRC_HSI14 + 1) |
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#define | STM32_SRC_PCLK (STM32_SRC_HSI48 + 1) |
| Bus clock.
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#define | STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1) |
| PLL clock.
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#define | CFGR1_REG 0x04 |
| RCC_CFGRx register offset.
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#define | CFGR3_REG 0x30 |
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#define | BDCR_REG 0x20 |
| RCC_BDCR register offset.
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#define | USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG) |
| Device domain clocks selection helpers.
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#define | I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG) |
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#define | CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG) |
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#define | USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 7, CFGR3_REG) |
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#define | USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG) |
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#define | USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG) |
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#define | RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) |
| BDCR devices.
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#define | MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) |
| CFGR1 devices.
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#define | MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) |
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◆ BDCR_REG
RCC_BDCR register offset.
◆ CEC_SEL
◆ CFGR1_REG
RCC_CFGRx register offset.
◆ CFGR3_REG
◆ I2C1_SEL
◆ MCO1_PRE
◆ MCO1_SEL
◆ RTC_SEL
◆ STM32_CLOCK_BUS_AHB1
#define STM32_CLOCK_BUS_AHB1 0x014 |
◆ STM32_CLOCK_BUS_APB1
#define STM32_CLOCK_BUS_APB1 0x01c |
◆ STM32_CLOCK_BUS_APB2
#define STM32_CLOCK_BUS_APB2 0x018 |
◆ STM32_PERIPH_BUS_MAX
◆ STM32_PERIPH_BUS_MIN
◆ STM32_SRC_HSI
Domain clocks.
System clock Fixed clocks
◆ STM32_SRC_HSI14
◆ STM32_SRC_HSI48
◆ STM32_SRC_PCLK
◆ STM32_SRC_PLLCLK
◆ USART1_SEL
Device domain clocks selection helpers.
CFGR3 devices
◆ USART2_SEL
◆ USART3_SEL
◆ USB_SEL