Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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stm32f0_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
8
10
12#define STM32_CLOCK_BUS_AHB1 0x014
13#define STM32_CLOCK_BUS_APB2 0x018
14#define STM32_CLOCK_BUS_APB1 0x01c
15
16#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
17#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
18
22/* defined in stm32_common_clocks.h */
24/* Low speed clocks defined in stm32_common_clocks.h */
25#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
26#define STM32_SRC_HSI14 (STM32_SRC_HSI + 1)
27#define STM32_SRC_HSI48 (STM32_SRC_HSI14 + 1)
29#define STM32_SRC_PCLK (STM32_SRC_HSI48 + 1)
31#define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1)
32
33#define STM32_CLOCK_REG_MASK 0xFFU
34#define STM32_CLOCK_REG_SHIFT 0U
35#define STM32_CLOCK_SHIFT_MASK 0x1FU
36#define STM32_CLOCK_SHIFT_SHIFT 8U
37#define STM32_CLOCK_MASK_MASK 0x7U
38#define STM32_CLOCK_MASK_SHIFT 13U
39#define STM32_CLOCK_VAL_MASK 0x7U
40#define STM32_CLOCK_VAL_SHIFT 16U
41
55#define STM32_CLOCK(val, mask, shift, reg) \
56 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
57 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
58 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
59 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
60
62#define CFGR3_REG 0x30
63
65#define BDCR_REG 0x20
66
69#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG)
70#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG)
71#define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG)
72#define USB_SEL(val) STM32_CLOCK(val, 1, 7, CFGR3_REG)
73#define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG)
74#define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG)
76#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG)
77
78#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */