stm32c0_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_CLOCK_BUS_IOP   0x034
	Bus clocks.
#define	STM32_CLOCK_BUS_AHB1   0x038
#define	STM32_CLOCK_BUS_APB1   0x03c
#define	STM32_CLOCK_BUS_APB1_2   0x040
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_IOP
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1_2
#define	STM32_SRC_HSI48   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_HSE   (STM32_SRC_HSI48 + 1)
#define	STM32_SRC_PCLK   (STM32_SRC_HSE + 1)
	Peripheral bus clock.
#define	STM32_CLOCK_REG_MASK   0xFFU
#define	STM32_CLOCK_REG_SHIFT   0U
#define	STM32_CLOCK_SHIFT_MASK   0x1FU
#define	STM32_CLOCK_SHIFT_SHIFT   8U
#define	STM32_CLOCK_MASK_MASK   0x7U
#define	STM32_CLOCK_MASK_SHIFT   13U
#define	STM32_CLOCK_VAL_MASK   0x7U
#define	STM32_CLOCK_VAL_SHIFT   16U
#define	STM32_DOMAIN_CLOCK(val, mask, shift, reg)
	STM32 clock configuration bit field.
#define	CCIPR_REG   0x54
	RCC_CCIPR register offset.
#define	CSR1_REG   0x5C
	RCC_CSR1 register offset.
#define	CFGR1_REG   0x08
	RCC_CFGRx register offset.
#define	USART1_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
	Device domain clocks selection helpers.
#define	I2C1_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
#define	I2C2_I2S1_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
#define	ADC_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
#define	RTC_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG)
	CSR1 devices.
#define	MCO1_SEL(val)   STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)
	CFGR1 devices.
#define	MCO1_PRE(val)   STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
#define	MCO2_SEL(val)   STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG)
#define	MCO2_PRE(val)   STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG)
#define	MCO_PRE_DIV_1   0
#define	MCO_PRE_DIV_2   1
#define	MCO_PRE_DIV_4   2
#define	MCO_PRE_DIV_8   3
#define	MCO_PRE_DIV_16   4
#define	MCO_PRE_DIV_32   5
#define	MCO_PRE_DIV_64   6
#define	MCO_PRE_DIV_128   7

Macro Definition Documentation

ADC_SEL

#define ADC_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)

CCIPR_REG

#define CCIPR_REG   0x54

RCC_CCIPR register offset.

CFGR1_REG

#define CFGR1_REG   0x08

RCC_CFGRx register offset.

CSR1_REG

#define CSR1_REG   0x5C

RCC_CSR1 register offset.

I2C1_SEL

#define I2C1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)

I2C2_I2S1_SEL

#define I2C2_I2S1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)

MCO1_PRE

#define MCO1_PRE

(

val

)

STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)

CFGR1 devices.

MCO2_PRE

#define MCO2_PRE

(

val

)

STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG)

MCO2_SEL

#define MCO2_SEL

(

val

)

STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG)

MCO_PRE_DIV_1

#define MCO_PRE_DIV_1   0

MCO_PRE_DIV_128

#define MCO_PRE_DIV_128   7

MCO_PRE_DIV_16

#define MCO_PRE_DIV_16   4

MCO_PRE_DIV_2

#define MCO_PRE_DIV_2   1

MCO_PRE_DIV_32

#define MCO_PRE_DIV_32   5

MCO_PRE_DIV_4

#define MCO_PRE_DIV_4   2

MCO_PRE_DIV_64

#define MCO_PRE_DIV_64   6

MCO_PRE_DIV_8

#define MCO_PRE_DIV_8   3

RTC_SEL

#define RTC_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG)

CSR1 devices.

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x038

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x03c

STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x040

STM32_CLOCK_BUS_IOP

#define STM32_CLOCK_BUS_IOP   0x034

Bus clocks.

STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

STM32_DOMAIN_CLOCK

#define STM32_DOMAIN_CLOCK	(		val,
			mask,
			shift,
			reg
	)

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32 clock configuration bit field.

• reg (1/2/3) [ 0 : 7 ]
• shift (0..31) [ 8 : 12 ]
• mask (0x1, 0x3, 0x7) [ 13 : 15 ]
• val (0..7) [ 16 : 18 ]

Parameters

reg	RCC_CCIPRx register offset
shift	Position within RCC_CCIPRx.
mask	Mask for the RCC_CCIPRx field.
val	Clock value (0, 1, ... 7).

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1_2

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_IOP

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_HSI48 + 1)

STM32_SRC_HSI48

#define STM32_SRC_HSI48   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_PCLK

#define STM32_SRC_PCLK   (STM32_SRC_HSE + 1)

Peripheral bus clock.

USART1_SEL

#define USART1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)

Device domain clocks selection helpers.

CCIPR devices