Zephyr Project API 4.1.99
A Scalable Open Source RTOS
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#include "stm32_common_clocks.h"
Go to the source code of this file.
Macros | |
#define | STM32_CLOCK_BUS_IOP 0x034 |
Bus clocks. | |
#define | STM32_CLOCK_BUS_AHB1 0x038 |
#define | STM32_CLOCK_BUS_APB1 0x03c |
#define | STM32_CLOCK_BUS_APB1_2 0x040 |
#define | STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP |
#define | STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2 |
#define | STM32_SRC_HSI (STM32_SRC_LSI + 1) |
Domain clocks. | |
#define | STM32_SRC_HSE (STM32_SRC_HSI + 1) |
#define | STM32_SRC_PCLK (STM32_SRC_HSE + 1) |
Peripheral bus clock. | |
#define | CCIPR_REG 0x54 |
RCC_CCIPR register offset. | |
#define | CCIPR2_REG 0x58 |
#define | CSR1_REG 0x5C |
RCC_CSR1 register offset. | |
#define | CFGR1_REG 0x08 |
RCC_CFGRx register offset. | |
#define | USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) |
Device domain clocks selection helpers. | |
#define | I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) |
#define | I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) |
#define | ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) |
#define | USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) |
CCIPR2 devices. | |
#define | RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG) |
CSR1 devices. | |
#define | MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG) |
CFGR1 devices. | |
#define | MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) |
#define | MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 16, CFGR1_REG) |
#define | MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 20, CFGR1_REG) |
#define | MCO_PRE_DIV_1 0 |
#define | MCO_PRE_DIV_2 1 |
#define | MCO_PRE_DIV_4 2 |
#define | MCO_PRE_DIV_8 3 |
#define | MCO_PRE_DIV_16 4 |
#define | MCO_PRE_DIV_32 5 |
#define | MCO_PRE_DIV_64 6 |
#define | MCO_PRE_DIV_128 7 |
#define ADC_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) |
#define CCIPR2_REG 0x58 |
#define CCIPR_REG 0x54 |
RCC_CCIPR register offset.
#define CFGR1_REG 0x08 |
RCC_CFGRx register offset.
#define CSR1_REG 0x5C |
RCC_CSR1 register offset.
#define I2C1_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) |
#define I2C2_I2S1_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) |
#define MCO1_PRE | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) |
#define MCO1_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG) |
CFGR1 devices.
#define MCO2_PRE | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 0x7, 20, CFGR1_REG) |
#define MCO2_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 0x7, 16, CFGR1_REG) |
#define MCO_PRE_DIV_1 0 |
#define MCO_PRE_DIV_128 7 |
#define MCO_PRE_DIV_16 4 |
#define MCO_PRE_DIV_2 1 |
#define MCO_PRE_DIV_32 5 |
#define MCO_PRE_DIV_4 2 |
#define MCO_PRE_DIV_64 6 |
#define MCO_PRE_DIV_8 3 |
#define RTC_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG) |
CSR1 devices.
#define STM32_CLOCK_BUS_AHB1 0x038 |
#define STM32_CLOCK_BUS_APB1 0x03c |
#define STM32_CLOCK_BUS_APB1_2 0x040 |
#define STM32_CLOCK_BUS_IOP 0x034 |
Bus clocks.
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2 |
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP |
#define STM32_SRC_HSE (STM32_SRC_HSI + 1) |
#define STM32_SRC_HSI (STM32_SRC_LSI + 1) |
Domain clocks.
System clock Fixed clocks
#define STM32_SRC_PCLK (STM32_SRC_HSE + 1) |
Peripheral bus clock.
#define USART1_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) |
Device domain clocks selection helpers.
CCIPR devices
#define USB_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) |
CCIPR2 devices.