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#define | STM32_CLOCK_BUS_IOP 0x034 |
| Bus clocks.
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#define | STM32_CLOCK_BUS_AHB1 0x038 |
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#define | STM32_CLOCK_BUS_APB1 0x03c |
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#define | STM32_CLOCK_BUS_APB1_2 0x040 |
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#define | STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP |
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#define | STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2 |
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#define | STM32_SRC_HSI (STM32_SRC_LSI + 1) |
| Domain clocks.
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#define | STM32_SRC_HSI48 (STM32_SRC_HSI + 1) |
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#define | STM32_SRC_HSE (STM32_SRC_HSI48 + 1) |
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#define | STM32_SRC_PCLK (STM32_SRC_HSE + 1) |
| Peripheral bus clock.
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#define | STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK + 1) |
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#define | CCIPR_REG 0x54 |
| RCC_CCIPR register offset.
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#define | CCIPR2_REG 0x58 |
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#define | CSR1_REG 0x5C |
| RCC_CSR1 register offset.
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#define | CFGR1_REG 0x08 |
| RCC_CFGRx register offset.
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#define | USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG) |
| Device domain clocks selection helpers.
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#define | FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG) |
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#define | I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG) |
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#define | I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG) |
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#define | ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG) |
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#define | USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR2_REG) |
| CCIPR2 devices.
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#define | RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG) |
| CSR1 devices.
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#define | MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xf, 24, CFGR1_REG) |
| CFGR1 devices.
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#define | MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 28, CFGR1_REG) |
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#define | MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xf, 16, CFGR1_REG) |
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#define | MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 20, CFGR1_REG) |
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#define | MCO_PRE_DIV_1 0 |
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#define | MCO_PRE_DIV_2 1 |
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#define | MCO_PRE_DIV_4 2 |
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#define | MCO_PRE_DIV_8 3 |
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#define | MCO_PRE_DIV_16 4 |
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#define | MCO_PRE_DIV_32 5 |
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#define | MCO_PRE_DIV_64 6 |
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#define | MCO_PRE_DIV_128 7 |
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