Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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stm32c0_clock.h
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1/*
2 * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_
8
10
12#define STM32_CLOCK_BUS_IOP 0x034
13#define STM32_CLOCK_BUS_AHB1 0x038
14#define STM32_CLOCK_BUS_APB1 0x03c
15#define STM32_CLOCK_BUS_APB1_2 0x040
16
17#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
18#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
19
21/* RM0490, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */
22
24/* defined in stm32_common_clocks.h */
26/* Low speed clocks defined in stm32_common_clocks.h */
27#define STM32_SRC_HSI48 (STM32_SRC_LSI + 1)
28#define STM32_SRC_HSE (STM32_SRC_HSI48 + 1)
30#define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
31
32#define STM32_CLOCK_REG_MASK 0xFFU
33#define STM32_CLOCK_REG_SHIFT 0U
34#define STM32_CLOCK_SHIFT_MASK 0x1FU
35#define STM32_CLOCK_SHIFT_SHIFT 8U
36#define STM32_CLOCK_MASK_MASK 0x7U
37#define STM32_CLOCK_MASK_SHIFT 13U
38#define STM32_CLOCK_VAL_MASK 0x7U
39#define STM32_CLOCK_VAL_SHIFT 16U
40
54#define STM32_CLOCK(val, mask, shift, reg) \
55 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
56 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
57 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
58 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
59
61#define CCIPR_REG 0x54
62
64#define CSR1_REG 0x5C
65
68#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
69#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
70#define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
71#define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
73#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, CSR1_REG)
74
75#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */