stm32f3_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_CLOCK_BUS_AHB1   0x014
	Bus gatting clocks.
#define	STM32_CLOCK_BUS_APB2   0x018
#define	STM32_CLOCK_BUS_APB1   0x01c
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1
#define	STM32_SRC_HSI   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_PCLK   (STM32_SRC_HSI + 1)
	Bus clock.
#define	STM32_SRC_PLLCLK   (STM32_SRC_PCLK + 1)
	PLL clock.
#define	STM32_CLOCK_REG_MASK   0xFFU
#define	STM32_CLOCK_REG_SHIFT   0U
#define	STM32_CLOCK_SHIFT_MASK   0x1FU
#define	STM32_CLOCK_SHIFT_SHIFT   8U
#define	STM32_CLOCK_MASK_MASK   0x7U
#define	STM32_CLOCK_MASK_SHIFT   13U
#define	STM32_CLOCK_VAL_MASK   0x7U
#define	STM32_CLOCK_VAL_SHIFT   16U
#define	STM32_DOMAIN_CLOCK(val, mask, shift, reg)
	STM32 clock configuration bit field.
#define	CFGR_REG   0x04
	RCC_CFGRx register offset.
#define	CFGR3_REG   0x30
#define	BDCR_REG   0x20
	RCC_BDCR register offset.
#define	I2S_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
	Device domain clocks selection helpers)
#define	MCO1_SEL(val)   STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
#define	MCO1_PRE(val)   STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG)
#define	USART1_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
	CFGR3 devices.
#define	I2C1_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
#define	I2C2_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG)
#define	I2C3_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
#define	TIM1_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG)
#define	TIM8_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG)
#define	TIM15_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG)
#define	TIM16_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG)
#define	TIM17_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 13, CFGR3_REG)
#define	TIM20_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 15, CFGR3_REG)
#define	USART2_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)
#define	USART3_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)
#define	USART4_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 20, CFGR3_REG)
#define	USART5_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 22, CFGR3_REG)
#define	TIM2_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 24, CFGR3_REG)
#define	TIM3_4_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 25, CFGR3_REG)
#define	RTC_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
	BDCR devices.

Macro Definition Documentation

BDCR_REG

#define BDCR_REG   0x20

RCC_BDCR register offset.

CFGR3_REG

#define CFGR3_REG   0x30

CFGR_REG

#define CFGR_REG   0x04

RCC_CFGRx register offset.

I2C1_SEL

#define I2C1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)

I2C2_SEL

#define I2C2_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG)

I2C3_SEL

#define I2C3_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)

I2S_SEL

#define I2S_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)

Device domain clocks selection helpers)

CFGR devices

MCO1_PRE

#define MCO1_PRE

(

val

)

STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)

RTC_SEL

#define RTC_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)

BDCR devices.

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x014

Bus gatting clocks.

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x01c

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x018

STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

STM32_DOMAIN_CLOCK

#define STM32_DOMAIN_CLOCK	(		val,
			mask,
			shift,
			reg
	)

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32 clock configuration bit field.

• reg (1/2/3) [ 0 : 7 ]
• shift (0..31) [ 8 : 12 ]
• mask (0x1, 0x3, 0x7) [ 13 : 15 ]
• val (0..7) [ 16 : 18 ]

Parameters

reg	RCC_CFGRx register offset
shift	Position within RCC_CFGRx.
mask	Mask for the RCC_CFGRx field.
val	Clock value (0, 1, ... 7).

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_PCLK

#define STM32_SRC_PCLK   (STM32_SRC_HSI + 1)

Bus clock.

STM32_SRC_PLLCLK

#define STM32_SRC_PLLCLK   (STM32_SRC_PCLK + 1)

PLL clock.

TIM15_SEL

#define TIM15_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG)

TIM16_SEL

#define TIM16_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG)

TIM17_SEL

#define TIM17_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 13, CFGR3_REG)

TIM1_SEL

#define TIM1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG)

TIM20_SEL

#define TIM20_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 15, CFGR3_REG)

TIM2_SEL

#define TIM2_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 24, CFGR3_REG)

TIM3_4_SEL

#define TIM3_4_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 25, CFGR3_REG)

TIM8_SEL

#define TIM8_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG)

USART1_SEL

#define USART1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)

CFGR3 devices.

USART2_SEL

#define USART2_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)

USART3_SEL

#define USART3_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)

USART4_SEL

#define USART4_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 20, CFGR3_REG)

USART5_SEL

#define USART5_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 22, CFGR3_REG)