Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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stm32f3_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
8
10
12#define STM32_CLOCK_BUS_AHB1 0x014
13#define STM32_CLOCK_BUS_APB2 0x018
14#define STM32_CLOCK_BUS_APB1 0x01c
15
16#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
17#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
18
20/* RM0316, ยง9.4.13 Clock configuration register (RCC_CFGR3) */
21
23/* Defined in stm32_common_clocks.h */
24
26/* Low speed clocks defined in stm32_common_clocks.h */
27#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
28/* #define STM32_SRC_HSI48 TDB */
30#define STM32_SRC_PCLK (STM32_SRC_HSI + 1)
32#define STM32_SRC_PLLCLK (STM32_SRC_PCLK + 1)
33
34#define STM32_CLOCK_REG_MASK 0xFFU
35#define STM32_CLOCK_REG_SHIFT 0U
36#define STM32_CLOCK_SHIFT_MASK 0x1FU
37#define STM32_CLOCK_SHIFT_SHIFT 8U
38#define STM32_CLOCK_MASK_MASK 0x7U
39#define STM32_CLOCK_MASK_SHIFT 13U
40#define STM32_CLOCK_VAL_MASK 0x7U
41#define STM32_CLOCK_VAL_SHIFT 16U
42
56#define STM32_CLOCK(val, mask, shift, reg) \
57 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
58 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
59 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
60 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
61
63#define CFGR_REG 0x04
64#define CFGR3_REG 0x30
65
67#define BDCR_REG 0x20
68
71#define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG)
73#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG)
74#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG)
75#define I2C2_SEL(val) STM32_CLOCK(val, 1, 5, CFGR3_REG)
76#define I2C3_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG)
77#define TIM1_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG)
78#define TIM8_SEL(val) STM32_CLOCK(val, 1, 9, CFGR3_REG)
79#define TIM15_SEL(val) STM32_CLOCK(val, 1, 10, CFGR3_REG)
80#define TIM16_SEL(val) STM32_CLOCK(val, 1, 11, CFGR3_REG)
81#define TIM17_SEL(val) STM32_CLOCK(val, 1, 13, CFGR3_REG)
82#define TIM20_SEL(val) STM32_CLOCK(val, 1, 15, CFGR3_REG)
83#define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG)
84#define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG)
85#define USART4_SEL(val) STM32_CLOCK(val, 3, 20, CFGR3_REG)
86#define USART5_SEL(val) STM32_CLOCK(val, 3, 22, CFGR3_REG)
87#define TIM2_SEL(val) STM32_CLOCK(val, 1, 24, CFGR3_REG)
88#define TIM3_4_SEL(val) STM32_CLOCK(val, 1, 25, CFGR3_REG)
90#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG)
91
92#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */