Go to the source code of this file.
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#define | STM32_CLOCK_BUS_AHB1 0x014 |
| Domain clocks.
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#define | STM32_CLOCK_BUS_APB2 0x018 |
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#define | STM32_CLOCK_BUS_APB1 0x01c |
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#define | STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 |
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#define | STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1 |
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#define | STM32_SRC_HSI (STM32_SRC_LSI + 1) |
| System clock.
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#define | STM32_SRC_HSE (STM32_SRC_HSI + 1) |
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#define | STM32_SRC_EXT_HSE (STM32_SRC_HSE + 1) |
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#define | STM32_SRC_PLLCLK (STM32_SRC_EXT_HSE + 1) |
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#define | CFGR1_REG 0x04 |
| RCC_CFGRx register offset.
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#define | CFGR2_REG 0x2C |
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#define | BDCR_REG 0x20 |
| RCC_BDCR register offset.
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#define | I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 17, CFGR2_REG) |
| Device domain clocks selection helpers.
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#define | I2S3_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 18, CFGR2_REG) |
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#define | RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG) |
| BDCR devices.
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#define | MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG) |
| CFGR1 devices.
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◆ BDCR_REG
RCC_BDCR register offset.
◆ CFGR1_REG
RCC_CFGRx register offset.
◆ CFGR2_REG
◆ I2S2_SEL
Device domain clocks selection helpers.
CFGR2 devices
◆ I2S3_SEL
◆ MCO1_SEL
◆ RTC_SEL
◆ STM32_CLOCK_BUS_AHB1
#define STM32_CLOCK_BUS_AHB1 0x014 |
Domain clocks.
Bus clocks
◆ STM32_CLOCK_BUS_APB1
#define STM32_CLOCK_BUS_APB1 0x01c |
◆ STM32_CLOCK_BUS_APB2
#define STM32_CLOCK_BUS_APB2 0x018 |
◆ STM32_PERIPH_BUS_MAX
◆ STM32_PERIPH_BUS_MIN
◆ STM32_SRC_EXT_HSE
◆ STM32_SRC_HSE
◆ STM32_SRC_HSI
System clock.
Fixed clocks
◆ STM32_SRC_PLLCLK