stm32f1_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_CLOCK_BUS_AHB1   0x014
	Domain clocks.
#define	STM32_CLOCK_BUS_APB2   0x018
#define	STM32_CLOCK_BUS_APB1   0x01c
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1
#define	STM32_SRC_HSI   (STM32_SRC_LSI + 1)
	System clock.
#define	STM32_SRC_HSE   (STM32_SRC_HSI + 1)
#define	STM32_SRC_EXT_HSE   (STM32_SRC_HSE + 1)
#define	STM32_SRC_PLLCLK   (STM32_SRC_EXT_HSE + 1)
#define	STM32_SRC_TIMPCLK1   (STM32_SRC_PLLCLK + 1)
#define	STM32_SRC_TIMPCLK2   (STM32_SRC_TIMPCLK1 + 1)
#define	CFGR1_REG   0x04
	RCC_CFGRx register offset.
#define	CFGR2_REG   0x2C
#define	BDCR_REG   0x20
	RCC_BDCR register offset.
#define	ADC_PRE(val)   STM32_DT_CLOCK_SELECT((val), 15, 14, CFGR1_REG)
	Device domain clocks selection helpers.
#define	I2S2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 17, 17, CFGR2_REG)
	CFGR2 devices.
#define	I2S3_SEL(val)   STM32_DT_CLOCK_SELECT((val), 18, 18, CFGR2_REG)
#define	RTC_SEL(val)   STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)
	BDCR devices.
#define	MCO1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 26, 24, CFGR1_REG)
	CFGR1 devices.
#define	ADC_PRE_DIV_2   0
#define	ADC_PRE_DIV_4   1
#define	ADC_PRE_DIV_6   2
#define	ADC_PRE_DIV_8   3

Macro Definition Documentation

ADC_PRE

#define ADC_PRE

(

val

)

STM32_DT_CLOCK_SELECT((val), 15, 14, CFGR1_REG)

Device domain clocks selection helpers.

CFGR1 devices

ADC_PRE_DIV_2

#define ADC_PRE_DIV_2   0

ADC_PRE_DIV_4

#define ADC_PRE_DIV_4   1

ADC_PRE_DIV_6

#define ADC_PRE_DIV_6   2

ADC_PRE_DIV_8

#define ADC_PRE_DIV_8   3

BDCR_REG

#define BDCR_REG   0x20

RCC_BDCR register offset.

CFGR1_REG

#define CFGR1_REG   0x04

RCC_CFGRx register offset.

CFGR2_REG

#define CFGR2_REG   0x2C

I2S2_SEL

#define I2S2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 17, 17, CFGR2_REG)

CFGR2 devices.

I2S3_SEL

#define I2S3_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 18, 18, CFGR2_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 26, 24, CFGR1_REG)

CFGR1 devices.

RTC_SEL

#define RTC_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)

BDCR devices.

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x014

Domain clocks.

Bus clocks

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x01c

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x018

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_EXT_HSE

#define STM32_SRC_EXT_HSE   (STM32_SRC_HSE + 1)

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_HSI + 1)

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

System clock.

Fixed clocks

STM32_SRC_PLLCLK

#define STM32_SRC_PLLCLK   (STM32_SRC_EXT_HSE + 1)

STM32_SRC_TIMPCLK1

#define STM32_SRC_TIMPCLK1   (STM32_SRC_PLLCLK + 1)

STM32_SRC_TIMPCLK2

#define STM32_SRC_TIMPCLK2   (STM32_SRC_TIMPCLK1 + 1)