Zephyr Project API 4.1.99
A Scalable Open Source RTOS
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stm32g0_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
8
10
12#define STM32_CLOCK_BUS_IOP 0x034
13#define STM32_CLOCK_BUS_AHB1 0x038
14#define STM32_CLOCK_BUS_APB1 0x03c
15#define STM32_CLOCK_BUS_APB1_2 0x040
16
17#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
18#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
19
21/* RM0444, ยง5.4.21/22 Clock configuration register (RCC_CCIPRx) */
22
24/* defined in stm32_common_clocks.h */
26/* Low speed clocks defined in stm32_common_clocks.h */
27#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
28#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
29#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
30#define STM32_SRC_HSE (STM32_SRC_MSI + 1)
32#define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
34#define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1)
35#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
36#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
37
39#define CFGR_REG 0x08
40
42#define CCIPR_REG 0x54
43#define CCIPR2_REG 0x58
44
46#define BDCR_REG 0x5C
47
50#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 24, CFGR_REG)
51#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 28, CFGR_REG)
52#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 16, CFGR_REG)
53#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 20, CFGR_REG)
55#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
56#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
57#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)
58#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR_REG)
59#define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
60#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
61#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
62#define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
63#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
64#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
65#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 22, CCIPR_REG)
66#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG)
67#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
68#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
70#define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
71#define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG)
72#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG)
73#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
75#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
76
77/* MCO prescaler : division factor */
78#define MCO_PRE_DIV_1 0
79#define MCO_PRE_DIV_2 1
80#define MCO_PRE_DIV_4 2
81#define MCO_PRE_DIV_8 3
82#define MCO_PRE_DIV_16 4
83#define MCO_PRE_DIV_32 5
84#define MCO_PRE_DIV_64 6
85#define MCO_PRE_DIV_128 7
86
87/* MCO clock output */
88#define MCO_SEL_SYSCLK 1
89#define MCO_SEL_HSI16 3
90#define MCO_SEL_HSE 4
91#define MCO_SEL_PLLRCLK 5
92#define MCO_SEL_LSI 6
93#define MCO_SEL_LSE 7
94
95#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */