Zephyr Project API
4.2.99
A Scalable Open Source RTOS
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stm32g0_clock.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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#define STM32_CLOCK_BUS_IOP 0x034
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#define STM32_CLOCK_BUS_AHB1 0x038
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#define STM32_CLOCK_BUS_APB1 0x03c
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#define STM32_CLOCK_BUS_APB1_2 0x040
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
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/* RM0444, ยง5.4.21/22 Clock configuration register (RCC_CCIPRx) */
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/* defined in stm32_common_clocks.h */
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/* Low speed clocks defined in stm32_common_clocks.h */
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#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
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#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
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#define STM32_SRC_HSE (STM32_SRC_MSI + 1)
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#define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
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#define STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK + 1)
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#define STM32_SRC_PLL_P (STM32_SRC_TIMPCLK1 + 1)
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#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
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#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
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#define CFGR_REG 0x08
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#define CCIPR_REG 0x54
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#define CCIPR2_REG 0x58
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#define BDCR_REG 0x5C
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 24, CFGR_REG)
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#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 28, CFGR_REG)
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#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 16, CFGR_REG)
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#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 20, CFGR_REG)
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#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
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#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
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#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)
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#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR_REG)
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#define LPUART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
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#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
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#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
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#define I2C2_I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
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#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
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#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
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#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 22, CCIPR_REG)
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#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG)
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#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
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#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
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#define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
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#define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG)
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#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG)
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#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
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/* MCO prescaler : division factor */
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#define MCO_PRE_DIV_1 0
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#define MCO_PRE_DIV_2 1
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#define MCO_PRE_DIV_4 2
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#define MCO_PRE_DIV_8 3
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#define MCO_PRE_DIV_16 4
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#define MCO_PRE_DIV_32 5
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#define MCO_PRE_DIV_64 6
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#define MCO_PRE_DIV_128 7
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/* MCO clock output */
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#define MCO_SEL_SYSCLK 1
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#define MCO_SEL_HSI16 3
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#define MCO_SEL_HSE 4
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#define MCO_SEL_PLLRCLK 5
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#define MCO_SEL_LSI 6
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#define MCO_SEL_LSE 7
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */
stm32_common_clocks.h
include
zephyr
dt-bindings
clock
stm32g0_clock.h
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