Zephyr Project API 3.7.0
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
stm32g0_clock.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
8
10
12#define STM32_CLOCK_BUS_IOP 0x034
13#define STM32_CLOCK_BUS_AHB1 0x038
14#define STM32_CLOCK_BUS_APB1 0x03c
15#define STM32_CLOCK_BUS_APB1_2 0x040
16
17#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
18#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2
19
21/* RM0444, ยง5.4.21/22 Clock configuration register (RCC_CCIPRx) */
22
24/* defined in stm32_common_clocks.h */
26/* Low speed clocks defined in stm32_common_clocks.h */
27#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
28#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
29#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
30#define STM32_SRC_HSE (STM32_SRC_MSI + 1)
32#define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
34#define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1)
35#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
36#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
37
38#define STM32_CLOCK_REG_MASK 0xFFU
39#define STM32_CLOCK_REG_SHIFT 0U
40#define STM32_CLOCK_SHIFT_MASK 0x1FU
41#define STM32_CLOCK_SHIFT_SHIFT 8U
42#define STM32_CLOCK_MASK_MASK 0x7U
43#define STM32_CLOCK_MASK_SHIFT 13U
44#define STM32_CLOCK_VAL_MASK 0x7U
45#define STM32_CLOCK_VAL_SHIFT 16U
46
60#define STM32_CLOCK(val, mask, shift, reg) \
61 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
62 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
63 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
64 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
65
67#define CCIPR_REG 0x54
68#define CCIPR2_REG 0x58
69
71#define BDCR_REG 0x5C
72
75#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
76#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
77#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
78#define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR_REG)
79#define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
80#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
81#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
82#define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
83#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
84#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
85#define TIM1_SEL(val) STM32_CLOCK(val, 1, 22, CCIPR_REG)
86#define TIM15_SEL(val) STM32_CLOCK(val, 1, 24, CCIPR_REG)
87#define RNG_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
88#define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
90#define I2S1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG)
91#define I2S2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR2_REG)
92#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR2_REG)
93#define USB_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG)
95#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG)
96
97#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */