Zephyr Project API
4.4.99
A Scalable Open Source RTOS
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stm32h7_clock.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
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#include <
zephyr/dt-bindings/clock/stm32_common_clocks.h
>
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/* RM0468, Table 56 Kernel clock dictribution summary */
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/* defined in stm32_common_clocks.h */
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/* Low speed clocks defined in stm32_common_clocks.h */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI48 (STM32_SRC_HSE + 1)
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#define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1)
/* HSI + HSIKERON */
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#define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1)
/* CSI + CSIKERON */
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#define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1)
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#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
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#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
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#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
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#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
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#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
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#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
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#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
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#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
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#define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1)
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#define STM32_SRC_TIMPCLK1 (STM32_SRC_CKPER + 1)
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#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
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/* #define STM32_SRC_I2SCKIN TBD */
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/* #define STM32_SRC_SPDIFRX TBD */
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#define STM32_CLOCK_BUS_AHB3 0x0D4
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#define STM32_CLOCK_BUS_AHB1 0x0D8
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#define STM32_CLOCK_BUS_AHB2 0x0DC
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#define STM32_CLOCK_BUS_AHB4 0x0E0
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#define STM32_CLOCK_BUS_APB3 0x0E4
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#define STM32_CLOCK_BUS_APB1 0x0E8
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#define STM32_CLOCK_BUS_APB1_2 0x0EC
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#define STM32_CLOCK_BUS_APB2 0x0F0
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#define STM32_CLOCK_BUS_APB4 0x0F4
/* TBD: To remove ? */
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#define STM32_SRC_PCLK1 STM32_CLOCK_BUS_APB1
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#define STM32_SRC_PCLK2 STM32_CLOCK_BUS_APB2
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#define STM32_SRC_HCLK3 STM32_CLOCK_BUS_AHB3
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#define STM32_SRC_PCLK3 STM32_CLOCK_BUS_APB3
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#define STM32_SRC_PCLK4 STM32_CLOCK_BUS_APB4
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
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#define D1CCIPR_REG 0x4C
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#define D2CCIP1R_REG 0x50
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#define D2CCIP2R_REG 0x54
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#define D3CCIPR_REG 0x58
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#define BDCR_REG 0x70
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#define CFGR_REG 0x10
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#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, D1CCIPR_REG)
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#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, D1CCIPR_REG)
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#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 8, D1CCIPR_REG)
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#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, D1CCIPR_REG)
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#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, D1CCIPR_REG)
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/* Device domain clocks selection helpers (RM0468.pdf) */
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#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 4, D1CCIPR_REG)
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#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, D2CCIP1R_REG)
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#define SAI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 6, D2CCIP1R_REG)
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/* Device domain clocks selection helpers for SAI2A and SAI2B (RM0455.pdf) */
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#define SAI2A_SEL(val) SAI23_SEL(val)
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#define SAI2B_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 9, D2CCIP1R_REG)
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#define SPI123_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, D2CCIP1R_REG)
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#define SPI45_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 16, D2CCIP1R_REG)
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#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, D2CCIP1R_REG)
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#define DFSDM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, D2CCIP1R_REG)
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#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, D2CCIP1R_REG)
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#define SWP_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 31, D2CCIP1R_REG)
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#define USART2345678_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, D2CCIP2R_REG)
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#define USART16_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, D2CCIP2R_REG)
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#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, D2CCIP2R_REG)
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#define I2C123_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, D2CCIP2R_REG)
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#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, D2CCIP2R_REG)
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#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, D2CCIP2R_REG)
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#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 30, 28, D2CCIP2R_REG)
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#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, D3CCIPR_REG)
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#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, D3CCIPR_REG)
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#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 12, 10, D3CCIPR_REG)
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#define LPTIM345_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 13, D3CCIPR_REG)
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#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, D3CCIPR_REG)
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#define SAI4A_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 21, D3CCIPR_REG)
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#define SAI4B_SEL(val) STM32_DT_CLOCK_SELECT((val), 26, 24, D3CCIPR_REG)
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#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 30, 28, D3CCIPR_REG)
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)
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#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 21, 18, CFGR_REG)
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 22, CFGR_REG)
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#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 28, 25, CFGR_REG)
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#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CFGR_REG)
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/* MCO prescaler : division factor */
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#define MCO_PRE_DIV_1 1
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#define MCO_PRE_DIV_2 2
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#define MCO_PRE_DIV_3 3
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#define MCO_PRE_DIV_4 4
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#define MCO_PRE_DIV_5 5
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#define MCO_PRE_DIV_6 6
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#define MCO_PRE_DIV_7 7
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#define MCO_PRE_DIV_8 8
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#define MCO_PRE_DIV_9 9
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#define MCO_PRE_DIV_10 10
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#define MCO_PRE_DIV_11 11
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#define MCO_PRE_DIV_12 12
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#define MCO_PRE_DIV_13 13
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#define MCO_PRE_DIV_14 14
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#define MCO_PRE_DIV_15 15
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/* MCO1 clock output */
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#define MCO1_SEL_HSI 0
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#define MCO1_SEL_LSE 1
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#define MCO1_SEL_HSE 2
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#define MCO1_SEL_PLL1QCLK 3
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#define MCO1_SEL_HSI48 4
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/* MCO2 clock output */
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#define MCO2_SEL_SYSCLK 0
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#define MCO2_SEL_PLL2PCLK 1
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#define MCO2_SEL_HSE 2
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#define MCO2_SEL_PLL1PCLK 3
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#define MCO2_SEL_CSI 4
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#define MCO2_SEL_LSI 5
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */
stm32_common_clocks.h
include
zephyr
dt-bindings
clock
stm32h7_clock.h
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