Zephyr Project API
4.1.0
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
stm32h7_clock.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2022 Linaro Limited
3
*
4
* SPDX-License-Identifier: Apache-2.0
5
*/
6
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
7
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
8
9
#include "
stm32_common_clocks.h
"
10
13
/* RM0468, Table 56 Kernel clock dictribution summary */
14
16
/* defined in stm32_common_clocks.h */
17
19
/* Low speed clocks defined in stm32_common_clocks.h */
20
#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
21
#define STM32_SRC_HSI48 (STM32_SRC_HSE + 1)
22
#define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1)
/* HSI + HSIKERON */
23
#define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1)
/* CSI + CSIKERON */
25
#define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1)
26
#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
27
#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
28
#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
29
#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
30
#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
31
#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
32
#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
33
#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
35
#define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1)
37
/* #define STM32_SRC_I2SCKIN TBD */
38
/* #define STM32_SRC_SPDIFRX TBD */
39
40
42
#define STM32_CLOCK_BUS_AHB3 0x0D4
43
#define STM32_CLOCK_BUS_AHB1 0x0D8
44
#define STM32_CLOCK_BUS_AHB2 0x0DC
45
#define STM32_CLOCK_BUS_AHB4 0x0E0
46
#define STM32_CLOCK_BUS_APB3 0x0E4
47
#define STM32_CLOCK_BUS_APB1 0x0E8
48
#define STM32_CLOCK_BUS_APB1_2 0x0EC
49
#define STM32_CLOCK_BUS_APB2 0x0F0
50
#define STM32_CLOCK_BUS_APB4 0x0F4
/* TBD: To remove ? */
52
#define STM32_SRC_PCLK1 STM32_CLOCK_BUS_APB1
53
#define STM32_SRC_PCLK2 STM32_CLOCK_BUS_APB2
54
#define STM32_SRC_HCLK3 STM32_CLOCK_BUS_AHB3
55
#define STM32_SRC_PCLK3 STM32_CLOCK_BUS_APB3
56
#define STM32_SRC_PCLK4 STM32_CLOCK_BUS_APB4
57
58
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
59
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
60
62
#define D1CCIPR_REG 0x4C
63
#define D2CCIP1R_REG 0x50
64
#define D2CCIP2R_REG 0x54
65
#define D3CCIPR_REG 0x58
66
68
#define BDCR_REG 0x70
69
71
#define CFGR_REG 0x10
72
75
#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, D1CCIPR_REG)
76
#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
77
#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, D1CCIPR_REG)
78
#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, D1CCIPR_REG)
79
#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG)
80
/* Device domain clocks selection helpers (RM0468.pdf) */
81
#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
83
#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIP1R_REG)
84
#define SAI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, D2CCIP1R_REG)
85
#define SPI123_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, D2CCIP1R_REG)
86
#define SPI45_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, D2CCIP1R_REG)
87
#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, D2CCIP1R_REG)
88
#define DFSDM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, D2CCIP1R_REG)
89
#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D2CCIP1R_REG)
90
#define SWP_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, D2CCIP1R_REG)
92
#define USART2345678_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIP2R_REG)
93
#define USART16_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 3, D2CCIP2R_REG)
94
#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, D2CCIP2R_REG)
95
#define I2C123_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIP2R_REG)
96
#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, D2CCIP2R_REG)
97
#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, D2CCIP2R_REG)
98
#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, D2CCIP2R_REG)
100
#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D3CCIPR_REG)
101
#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, D3CCIPR_REG)
102
#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 10, D3CCIPR_REG)
103
#define LPTIM345_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 13, D3CCIPR_REG)
104
#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, D3CCIPR_REG)
105
#define SAI4A_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 21, D3CCIPR_REG)
106
#define SAI4B_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, D3CCIPR_REG)
107
#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, D3CCIPR_REG)
109
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
111
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 22, CFGR_REG)
112
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 18, CFGR_REG)
113
#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 29, CFGR_REG)
114
#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 25, CFGR_REG)
115
116
/* MCO prescaler : division factor */
117
#define MCO_PRE_DIV_1 1
118
#define MCO_PRE_DIV_2 2
119
#define MCO_PRE_DIV_3 3
120
#define MCO_PRE_DIV_4 4
121
#define MCO_PRE_DIV_5 5
122
#define MCO_PRE_DIV_6 6
123
#define MCO_PRE_DIV_7 7
124
#define MCO_PRE_DIV_8 8
125
#define MCO_PRE_DIV_9 9
126
#define MCO_PRE_DIV_10 10
127
#define MCO_PRE_DIV_11 11
128
#define MCO_PRE_DIV_12 12
129
#define MCO_PRE_DIV_13 13
130
#define MCO_PRE_DIV_14 14
131
#define MCO_PRE_DIV_15 15
132
133
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */
stm32_common_clocks.h
include
zephyr
dt-bindings
clock
stm32h7_clock.h
Generated on Sat Apr 19 2025 20:06:32 for Zephyr Project API by
1.9.8
1.9.8