Zephyr Project API 4.2.99
A Scalable Open Source RTOS
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stm32h7_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
8
10
13/* RM0468, Table 56 Kernel clock dictribution summary */
14
16/* defined in stm32_common_clocks.h */
17
19/* Low speed clocks defined in stm32_common_clocks.h */
20#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
21#define STM32_SRC_HSI48 (STM32_SRC_HSE + 1)
22#define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */
23#define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1) /* CSI + CSIKERON */
25#define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1)
26#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
27#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
28#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
29#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
30#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
31#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
32#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
33#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
35#define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1)
37#define STM32_SRC_TIMPCLK1 (STM32_SRC_CKPER + 1)
38#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
40/* #define STM32_SRC_I2SCKIN TBD */
41/* #define STM32_SRC_SPDIFRX TBD */
42
43
45#define STM32_CLOCK_BUS_AHB3 0x0D4
46#define STM32_CLOCK_BUS_AHB1 0x0D8
47#define STM32_CLOCK_BUS_AHB2 0x0DC
48#define STM32_CLOCK_BUS_AHB4 0x0E0
49#define STM32_CLOCK_BUS_APB3 0x0E4
50#define STM32_CLOCK_BUS_APB1 0x0E8
51#define STM32_CLOCK_BUS_APB1_2 0x0EC
52#define STM32_CLOCK_BUS_APB2 0x0F0
53#define STM32_CLOCK_BUS_APB4 0x0F4
/* TBD: To remove ? */
55#define STM32_SRC_PCLK1 STM32_CLOCK_BUS_APB1
56#define STM32_SRC_PCLK2 STM32_CLOCK_BUS_APB2
57#define STM32_SRC_HCLK3 STM32_CLOCK_BUS_AHB3
58#define STM32_SRC_PCLK3 STM32_CLOCK_BUS_APB3
59#define STM32_SRC_PCLK4 STM32_CLOCK_BUS_APB4
60
61#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
62#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
63
65#define D1CCIPR_REG 0x4C
66#define D2CCIP1R_REG 0x50
67#define D2CCIP2R_REG 0x54
68#define D3CCIPR_REG 0x58
69
71#define BDCR_REG 0x70
72
74#define CFGR_REG 0x10
75
78#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, D1CCIPR_REG)
79#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
80#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 8, D1CCIPR_REG)
81#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, D1CCIPR_REG)
82#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG)
83/* Device domain clocks selection helpers (RM0468.pdf) */
84#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
86#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIP1R_REG)
87#define SAI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, D2CCIP1R_REG)
88#define SPI123_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, D2CCIP1R_REG)
89#define SPI45_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, D2CCIP1R_REG)
90#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, D2CCIP1R_REG)
91#define DFSDM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, D2CCIP1R_REG)
92#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 28, D2CCIP1R_REG)
93#define SWP_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, D2CCIP1R_REG)
95#define USART2345678_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIP2R_REG)
96#define USART16_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 3, D2CCIP2R_REG)
97#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, D2CCIP2R_REG)
98#define I2C123_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIP2R_REG)
99#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, D2CCIP2R_REG)
100#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, D2CCIP2R_REG)
101#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, D2CCIP2R_REG)
103#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, D3CCIPR_REG)
104#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, D3CCIPR_REG)
105#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 10, D3CCIPR_REG)
106#define LPTIM345_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 13, D3CCIPR_REG)
107#define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, D3CCIPR_REG)
108#define SAI4A_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 21, D3CCIPR_REG)
109#define SAI4B_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, D3CCIPR_REG)
110#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, D3CCIPR_REG)
112#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
114#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 22, CFGR_REG)
115#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 18, CFGR_REG)
116#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 29, CFGR_REG)
117#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 25, CFGR_REG)
118
119/* MCO prescaler : division factor */
120#define MCO_PRE_DIV_1 1
121#define MCO_PRE_DIV_2 2
122#define MCO_PRE_DIV_3 3
123#define MCO_PRE_DIV_4 4
124#define MCO_PRE_DIV_5 5
125#define MCO_PRE_DIV_6 6
126#define MCO_PRE_DIV_7 7
127#define MCO_PRE_DIV_8 8
128#define MCO_PRE_DIV_9 9
129#define MCO_PRE_DIV_10 10
130#define MCO_PRE_DIV_11 11
131#define MCO_PRE_DIV_12 12
132#define MCO_PRE_DIV_13 13
133#define MCO_PRE_DIV_14 14
134#define MCO_PRE_DIV_15 15
135
136#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */