Zephyr Project API
4.4.99
A Scalable Open Source RTOS
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stm32mp13_clock.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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/* defined in stm32_common_clocks.h */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
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#define STM32_SRC_PLL1_P (STM32_SRC_HSI + 1)
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#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_P + 1)
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#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
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#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
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#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
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#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
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#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
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#define STM32_SRC_PLL4_P (STM32_SRC_PLL3_R + 1)
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#define STM32_SRC_PLL4_Q (STM32_SRC_PLL4_P + 1)
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#define STM32_SRC_PLL4_R (STM32_SRC_PLL4_Q + 1)
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#define STM32_SRC_TIMPCLK1 (STM32_SRC_PLL4_R + 1)
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#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
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#define STM32_SRC_TIMPCLK6 (STM32_SRC_TIMPCLK2 + 1)
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#define STM32_CLOCK_BUS_APB1 0x700
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#define STM32_CLOCK_BUS_APB2 0x708
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#define STM32_CLOCK_BUS_APB3 0x710
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#define STM32_CLOCK_BUS_APB3_S 0x718
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#define STM32_CLOCK_BUS_APB4 0x728
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#define STM32_CLOCK_BUS_APB4_NS 0x738
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#define STM32_CLOCK_BUS_APB5 0x740
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#define STM32_CLOCK_BUS_APB6 0x748
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#define STM32_CLOCK_BUS_AHB2 0x750
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#define STM32_CLOCK_BUS_AHB4 0x768
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#define STM32_CLOCK_BUS_AHB5 0x778
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#define STM32_CLOCK_BUS_AHB6 0x780
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_APB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_AHB6
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#define BDCR_REG 0x400
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#define MCO1CFGR_REG 0x460
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#define MCO2CFGR_REG 0x464
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#define I2C12CKSELR_REG 0x600
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#define I2C345CKSELR_REG 0x604
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#define SPI2S1CKSELR_REG 0x608
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#define SPI2S23CKSELR_REG 0x60c
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#define SPI45CKSELR_REG 0x610
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#define UART12CKSELR_REG 0x614
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#define UART35CKSELR_REG 0x618
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#define UART4CKSELR_REG 0x61c
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#define UART6CKSELR_REG 0x620
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#define UART78CKSELR_REG 0x624
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#define LPTIM1CKSELR_REG 0x628
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#define LPTIM23CKSELR_REG 0x62c
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#define LPTIM45CKSELR_REG 0x630
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#define SAI1CKSELR_REG 0x634
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#define SAI2CKSELR_REG 0x638
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#define FDCANCKSELR_REG 0x63c
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#define SPDIFCKSELR_REG 0x640
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#define ADC12CKSELR_REG 0x644
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#define SDMMC12CKSELR_REG 0x648
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#define ETH12CKSELR_REG 0x64c
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#define USBCKSELR_REG 0x650
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#define QSPICKSELR_REG 0x654
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#define FMCCKSELR_REG 0x658
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#define RNG1CKSELR_REG 0x65c
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#define STGENCKSELR_REG 0x660
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#define DCMIPPCKSELR_REG 0x664
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#define SAESCKSELR_REG 0x668
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, MCO1CFGR_REG)
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#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 7, 4, MCO1CFGR_REG)
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#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, MCO2CFGR_REG)
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#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 7, 4, MCO2CFGR_REG)
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#define MCOX_ON BIT(12)
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/* MCO1 source */
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#define MCO1_SEL_HSI 0
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#define MCO1_SEL_HSE 1
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#define MCO1_SEL_CSI 2
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#define MCO1_SEL_LSI 3
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#define MCO1_SEL_LSE 4
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/* MCO2 source */
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#define MCO2_SEL_MPU 0
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#define MCO2_SEL_AXI 1
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#define MCO2_SEL_MLAHB 2
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#define MCO2_SEL_PLL4 3
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#define MCO2_SEL_HSE 4
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#define MCO2_SEL_HSI 5
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/* MCO prescaler : division factor */
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#define MCO_PRE_DIV_1 0
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#define MCO_PRE_DIV_2 1
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#define MCO_PRE_DIV_3 2
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#define MCO_PRE_DIV_4 3
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#define MCO_PRE_DIV_5 4
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#define MCO_PRE_DIV_6 5
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#define MCO_PRE_DIV_7 6
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#define MCO_PRE_DIV_8 7
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#define MCO_PRE_DIV_9 8
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#define MCO_PRE_DIV_10 9
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#define MCO_PRE_DIV_11 10
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#define MCO_PRE_DIV_12 11
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#define MCO_PRE_DIV_13 12
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#define MCO_PRE_DIV_14 13
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#define MCO_PRE_DIV_15 14
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#define MCO_PRE_DIV_16 15
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#define I2C12_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, I2C12CKSELR_REG)
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#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, I2C345CKSELR_REG)
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#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, I2C345CKSELR_REG)
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#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 6, I2C345CKSELR_REG)
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#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SPI2S1CKSELR_REG)
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#define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SPI2S23CKSELR_REG)
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#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SPI45CKSELR_REG)
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#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, SPI45CKSELR_REG)
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#define UART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART12CKSELR_REG)
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#define UART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, UART12CKSELR_REG)
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#define UART35_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART35CKSELR_REG)
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#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART4CKSELR_REG)
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#define UART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART6CKSELR_REG)
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#define UART78_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, UART78CKSELR_REG)
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#define LPTIME1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, LPTIM1CKSELR_REG)
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#define LPTIME2_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, LPTIM23CKSELR_REG)
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#define LPTIME3_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, LPTIM23CKSELR_REG)
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#define LPTIME45_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, LPTIM45CKSELR_REG)
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#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SAI1CKSELR_REG)
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#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SAI2CKSELR_REG)
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#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, FDCANCKSELR_REG)
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#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, SPDIFCKSELR_REG)
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#define ADC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, ADC12CKSELR_REG)
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#define ADC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, ADC12CKSELR_REG)
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#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, SDMMC12CKSELR_REG)
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#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 5, 3, SDMMC12CKSELR_REG)
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#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, ETH12CKSELR_REG)
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#define ETH2_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, ETH12CKSELR_REG)
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#define USBPHY_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, USBCKSELR_REG)
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#define USBOTG_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 4, USBCKSELR_REG)
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#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, QSPICKSELR_REG)
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#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, FMCCKSELR_REG)
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#define RNG1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, RNG1CKSELR_REG)
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#define STGEN_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, STGENCKSELR_REG)
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#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, DCMIPPCKSELR_REG)
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#define SAES_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, SAESCKSELR_REG)
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, BDCR_REG)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_ */
stm32_common_clocks.h
include
zephyr
dt-bindings
clock
stm32mp13_clock.h
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