Zephyr Project API 4.2.99
A Scalable Open Source RTOS
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stm32mp13_clock.h
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1/*
2 * Copyright (c) 2025 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_
8
10
12/* defined in stm32_common_clocks.h */
14#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
15#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
16
18#define STM32_SRC_PLL1_P (STM32_SRC_HSI + 1)
19#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_P + 1)
20#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
21#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
22#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
23#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
24#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
25#define STM32_SRC_PLL4_P (STM32_SRC_PLL3_R + 1)
26#define STM32_SRC_PLL4_Q (STM32_SRC_PLL4_P + 1)
27#define STM32_SRC_PLL4_R (STM32_SRC_PLL4_Q + 1)
28
30#define STM32_CLOCK_BUS_APB1 0x700
31#define STM32_CLOCK_BUS_APB2 0x708
32#define STM32_CLOCK_BUS_APB3 0x710
33#define STM32_CLOCK_BUS_APB3_S 0x718
34#define STM32_CLOCK_BUS_APB4 0x728
35#define STM32_CLOCK_BUS_APB4_NS 0x738
36#define STM32_CLOCK_BUS_APB5 0x740
37#define STM32_CLOCK_BUS_APB6 0x748
38#define STM32_CLOCK_BUS_AHB2 0x750
39#define STM32_CLOCK_BUS_AHB4 0x768
40#define STM32_CLOCK_BUS_AHB5 0x778
41#define STM32_CLOCK_BUS_AHB6 0x780
42
43#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_APB1
44#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_AHB6
45
47#define MCO1CFGR_REG 0x460
48#define MCO2CFGR_REG 0x464
49#define I2C12CKSELR_REG 0x600
50#define I2C345CKSELR_REG 0x604
51#define SPI2S1CKSELR_REG 0x608
52#define SPI2S23CKSELR_REG 0x60c
53#define SPI45CKSELR_REG 0x610
54#define UART12CKSELR_REG 0x614
55#define UART35CKSELR_REG 0x618
56#define UART4CKSELR_REG 0x61c
57#define UART6CKSELR_REG 0x620
58#define UART78CKSELR_REG 0x624
59#define LPTIM1CKSELR_REG 0x628
60#define LPTIM23CKSELR_REG 0x62c
61#define LPTIM45CKSELR_REG 0x630
62#define SAI1CKSELR_REG 0x634
63#define SAI2CKSELR_REG 0x638
64#define FDCANCKSELR_REG 0x63c
65#define SPDIFCKSELR_REG 0x640
66#define ADC12CKSELR_REG 0x644
67#define SDMMC12CKSELR_REG 0x648
68#define ETH12CKSELR_REG 0x64c
69#define USBCKSELR_REG 0x650
70#define QSPICKSELR_REG 0x654
71#define FMCCKSELR_REG 0x658
72#define RNG1CKSELR_REG 0x65c
73#define STGENCKSELR_REG 0x660
74#define DCMIPPCKSELR_REG 0x664
75#define SAESCKSELR_REG 0x668
76
78#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO1CFGR_REG)
79#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO1CFGR_REG)
80#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO2CFGR_REG)
81#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO2CFGR_REG)
82
83#define MCOX_ON BIT(12)
84
85/* MCO1 source */
86#define MCO1_SEL_HSI 0
87#define MCO1_SEL_HSE 1
88#define MCO1_SEL_CSI 2
89#define MCO1_SEL_LSI 3
90#define MCO1_SEL_LSE 4
91
92/* MCO2 source */
93#define MCO2_SEL_MPU 0
94#define MCO2_SEL_AXI 1
95#define MCO2_SEL_MLAHB 2
96#define MCO2_SEL_PLL4 3
97#define MCO2_SEL_HSE 4
98#define MCO2_SEL_HSI 5
99
100/* MCO prescaler : division factor */
101#define MCO_PRE_DIV_1 0
102#define MCO_PRE_DIV_2 1
103#define MCO_PRE_DIV_3 2
104#define MCO_PRE_DIV_4 3
105#define MCO_PRE_DIV_5 4
106#define MCO_PRE_DIV_6 5
107#define MCO_PRE_DIV_7 6
108#define MCO_PRE_DIV_8 7
109#define MCO_PRE_DIV_9 8
110#define MCO_PRE_DIV_10 9
111#define MCO_PRE_DIV_11 10
112#define MCO_PRE_DIV_12 11
113#define MCO_PRE_DIV_13 12
114#define MCO_PRE_DIV_14 13
115#define MCO_PRE_DIV_15 14
116#define MCO_PRE_DIV_16 15
117
118#define I2C12_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C12CKSELR_REG)
119#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C345CKSELR_REG)
120#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, I2C345CKSELR_REG)
121#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 6, I2C345CKSELR_REG)
122#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S1CKSELR_REG)
123#define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S23CKSELR_REG)
124#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI45CKSELR_REG)
125#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, SPI45CKSELR_REG)
126#define UART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART12CKSELR_REG)
127#define UART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, UART12CKSELR_REG)
128#define UART35_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART35CKSELR_REG)
129#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART4CKSELR_REG)
130#define UART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART6CKSELR_REG)
131#define UART78_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART78CKSELR_REG)
132#define LPTIME1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM1CKSELR_REG)
133#define LPTIME2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM23CKSELR_REG)
134#define LPTIME3_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, LPTIM23CKSELR_REG)
135#define LPTIME45_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM45CKSELR_REG)
136#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI1CKSELR_REG)
137#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI2CKSELR_REG)
138#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, FDCANCKSELR_REG)
139#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, SPDIFCKSELR_REG)
140#define ADC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, ADC12CKSELR_REG)
141#define ADC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 2, ADC12CKSELR_REG)
142#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SDMMC12CKSELR_REG)
143#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, SDMMC12CKSELR_REG)
144#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, ETH12CKSELR_REG)
145#define ETH2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 8, ETH12CKSELR_REG)
146#define USBPHY_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, USBCKSELR_REG)
147#define USBOTG_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x1, 4, USBCKSELR_REG)
148#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, QSPICKSELR_REG)
149#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, FMCCKSELR_REG)
150#define RNG1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, RNG1CKSELR_REG)
151#define STGEN_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, STGENCKSELR_REG)
152#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, DCMIPPCKSELR_REG)
153#define SAES_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, SAESCKSELR_REG)
154
155#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_ */