Zephyr Project API 4.2.99
A Scalable Open Source RTOS
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stm32u5_clock.h
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1/*
2 * Copyright (c) 2022 Linaro Limited
3 * Copyright (c) 2023 STMicroelectronics
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
8#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_
9
10#include "stm32_common_clocks.h"
11
14/* RM0456, Figure 36 Clock tree for STM32U5 Series */
15
17/* defined in stm32_common_clocks.h */
19#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
20#define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
21#define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1)
22#define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
23#define STM32_SRC_MSIK (STM32_SRC_MSIS + 1)
25#define STM32_SRC_HCLK (STM32_SRC_MSIK + 1)
26#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
27#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
28#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
29#define STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK3 + 1)
30#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
32#define STM32_SRC_PLL1_P (STM32_SRC_TIMPCLK2 + 1)
33#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
34#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
35#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
36#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
37#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
38#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
39#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
40#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
42/* #define STM32_SRC_ICLK TBD */
43
45#define STM32_CLOCK_BUS_AHB1 0x088
46#define STM32_CLOCK_BUS_AHB2 0x08C
47#define STM32_CLOCK_BUS_AHB2_2 0x090
48#define STM32_CLOCK_BUS_AHB3 0x094
49#define STM32_CLOCK_BUS_APB1 0x09C
50#define STM32_CLOCK_BUS_APB1_2 0x0A0
51#define STM32_CLOCK_BUS_APB2 0x0A4
52#define STM32_CLOCK_BUS_APB3 0x0A8
53
54#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
55#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
56
58#define CCIPR1_REG 0xE0
59#define CCIPR2_REG 0xE4
60#define CCIPR3_REG 0xE8
61
63#define BDCR_REG 0xF0
64
66#define CFGR1_REG 0x1C
67
70#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG)
71#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG)
72#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR1_REG)
73#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR1_REG)
74#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR1_REG)
75#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG)
76#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR1_REG)
77#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR1_REG)
78#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR1_REG)
79#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG)
80#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)
81#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)
82#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR1_REG)
83#define ICKLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR1_REG)
84#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 29, CCIPR1_REG)
86#define MDF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR2_REG)
87#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG)
88#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG)
89#define SAE_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CCIPR2_REG)
90#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
91#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG)
92#define DSIHOST_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR2_REG)
93#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR2_REG)
94#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 18, CCIPR2_REG)
95#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)
96#define HSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR2_REG)
97#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR2_REG)
98#define I2C6_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR2_REG)
99#define OTGHS_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR2_REG)
101#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR3_REG)
102#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG)
103#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG)
104#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR3_REG)
105#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG)
106#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG)
107#define DAC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR3_REG)
108#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR3_REG)
110#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
111
113#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
114#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
115
116/* MCO prescaler : division factor */
117#define MCO_PRE_DIV_1 0
118#define MCO_PRE_DIV_2 1
119#define MCO_PRE_DIV_4 2
120#define MCO_PRE_DIV_8 3
121#define MCO_PRE_DIV_16 4
122
123#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */