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Zephyr Project API 4.3.99
A Scalable Open Source RTOS
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Structure holding the configuration for the GPIO FIFO pulse width, polarity, and pins. More...
#include <gpio_bl61x_wo.h>
Data Fields | |
| uint16_t | total_cycles |
| Total clock cycles length of a toggling cycles (9 bits) | |
| uint8_t | set_cycles |
| Number of clock cycles a pin is toggled when its bit is set. | |
| uint8_t | unset_cycles |
| Number of clock cycles a pin is toggled when its bit is unset. | |
| bool | set_invert |
| Go from low to high instead of high to low when bit is set. | |
| bool | unset_invert |
| Same but when bit is unset. | |
| bool | park_high |
| Park pins high instead of low at the end of a sequence. | |
Structure holding the configuration for the GPIO FIFO pulse width, polarity, and pins.
Such as:
set_invert, unset_invert and park_high are false total_cycles is 9 set_cycles is 6 unset_cycles is 4 2 frames of data, one with the pin bit set to 1, one with it set to 0 The clock cycle unit is XCLK's speed (RC32M or crystal)
Pins match such as toggle bit = pin & 16 (eg, pin 0 is bit 0, 17 is bit 1, pin 2 is bit 2, etc).
| bool bl61x_wo_config::park_high |
Park pins high instead of low at the end of a sequence.
| uint8_t bl61x_wo_config::set_cycles |
Number of clock cycles a pin is toggled when its bit is set.
| bool bl61x_wo_config::set_invert |
Go from low to high instead of high to low when bit is set.
| uint16_t bl61x_wo_config::total_cycles |
Total clock cycles length of a toggling cycles (9 bits)
| uint8_t bl61x_wo_config::unset_cycles |
Number of clock cycles a pin is toggled when its bit is unset.
| bool bl61x_wo_config::unset_invert |
Same but when bit is unset.