15#ifndef ZEPHYR_INCLUDE_ARCH_X86_IA32_ARCH_H_
16#define ZEPHYR_INCLUDE_ARCH_X86_IA32_ARCH_H_
48#if defined(CONFIG_USERSPACE)
49#define GS_TLS_SEG (0x38 | 0x03)
50#elif defined(CONFIG_X86_STACK_PROTECTION)
51#define GS_TLS_SEG (0x28 | 0x03)
53#define GS_TLS_SEG (0x18 | 0x03)
60#define MK_ISR_NAME(x) __isr__##x
62#define Z_DYN_STUB_SIZE 4
63#define Z_DYN_STUB_OFFSET 0
64#define Z_DYN_STUB_LONG_JMP_EXTRA_SIZE 3
65#define Z_DYN_STUB_PER_BLOCK 32
122#define NANO_CPU_INT_REGISTER(r, n, p, v, d) \
123 static ISR_LIST __attribute__((section(".intList"))) \
124 __attribute__((used)) MK_ISR_NAME(r) = \
147#define _X86_IDT_TSS_REGISTER(tss_p, irq_p, priority_p, vec_p, dpl_p) \
148 static ISR_LIST __attribute__((section(".intList"))) \
149 __attribute__((used)) MK_ISR_NAME(vec_p) = \
153 .priority = (priority_p), \
173#define _VECTOR_ARG(irq_p) (-1)
175#ifdef CONFIG_LINKER_USE_PINNED_SECTION
176#define IRQSTUBS_TEXT_SECTION ".pinned_text.irqstubs"
178#define IRQSTUBS_TEXT_SECTION ".text.irqstubs"
199#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
201 __asm__ __volatile__( \
202 ".pushsection .intList\n\t" \
203 ".long %c[isr]_irq%c[irq]_stub\n\t" \
204 ".long %c[irq]\n\t" \
205 ".long %c[priority]\n\t" \
206 ".long %c[vector]\n\t" \
210 ".pushsection " IRQSTUBS_TEXT_SECTION "\n\t" \
211 ".global %c[isr]_irq%c[irq]_stub\n\t" \
212 "%c[isr]_irq%c[irq]_stub:\n\t" \
213 "pushl %[isr_param]\n\t" \
215 "jmp _interrupt_enter\n\t" \
218 : [isr] "i" (isr_p), \
219 [isr_param] "i" (isr_param_p), \
220 [priority] "i" (priority_p), \
221 [vector] "i" _VECTOR_ARG(irq_p), \
222 [irq] "i" (irq_p)); \
223 z_irq_controller_irq_config(Z_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), \
229#define ARCH_PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, \
230 isr_p, isr_param_p, flags_p) \
231 ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p)
242#ifndef CONFIG_X86_KPTI
243#define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
245 NANO_CPU_INT_REGISTER(isr_p, irq_p, priority_p, -1, 0); \
246 z_irq_controller_irq_config(Z_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), \
251static inline void arch_irq_direct_pm(
void)
259#define ARCH_ISR_DIRECT_PM() arch_irq_direct_pm()
261#define ARCH_ISR_DIRECT_PM() do { } while (false)
264#define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header()
265#define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap)
270#if defined(CONFIG_TRACING)
277#if defined(CONFIG_TRACING)
284 ++_kernel.cpus[0].nested;
296 z_irq_controller_eoi();
297#if defined(CONFIG_TRACING)
300 --_kernel.cpus[0].nested;
308 if (swap != 0 && _kernel.cpus[0].nested == 0 &&
309 _kernel.ready_q.cache != _current) {
325#define ARCH_ISR_DIRECT_DECLARE(name) \
326 static inline int name##_body(void); \
327 __attribute__ ((interrupt)) void name(void *stack_frame) \
329 ARG_UNUSED(stack_frame); \
330 int check_reschedule; \
331 ISR_DIRECT_HEADER(); \
332 check_reschedule = name##_body(); \
333 ISR_DIRECT_FOOTER(check_reschedule); \
335 static inline int name##_body(void)
342 __asm__
volatile (
"pushfl; cli; popl %0" :
"=g" (key) ::
"memory");
353#define NANO_SOFT_IRQ ((unsigned int) (-1))
355#ifdef CONFIG_X86_ENABLE_TSS
359#define ARCH_EXCEPT(reason_p) do { \
361 "push %[reason]\n\t" \
362 "int %[vector]\n\t" \
364 : [vector] "i" (Z_X86_OOPS_VECTOR), \
365 [reason] "i" (reason_p)); \
376#if defined(CONFIG_EAGER_FPU_SHARING) || defined(CONFIG_LAZY_FPU_SHARING)
378#define ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT 16
380#define ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT (sizeof(void *))
384#define ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT (sizeof(void *))
IA-32 specific gdbstub interface header.
x86 (IA32) specific syscall header
Per-arch thread definition.
void pm_system_resume(void)
Notify exit from kernel sleep.
void sys_trace_isr_enter(void)
Called when entering an ISR.
void sys_trace_isr_exit(void)
Called when exiting an ISR.
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
Definition arch.h:72
flags
Definition parser.h:97
unsigned int tss
If nonzero, specifies a TSS segment selector.
Definition arch.h:97
void * fnc
Address of ISR/stub.
Definition arch.h:78
unsigned int dpl
Privilege level associated with ISR/stub.
Definition arch.h:91
unsigned int irq
IRQ associated with the ISR/stub, or -1 if this is not associated with a real interrupt; in this case...
Definition arch.h:83
unsigned int vec
Vector number associated with ISR/stub, or -1 to assign based on priority.
Definition arch.h:89
unsigned int priority
Priority associated with the IRQ.
Definition arch.h:85
Definition segmentation.h:54
static void arch_isr_direct_footer(int swap)
Definition arch.h:294
void arch_isr_direct_footer_swap(unsigned int key)
struct s_isrList ISR_LIST
static void arch_isr_direct_header(void)
Definition arch.h:275