Zephyr Project API 4.1.99
A Scalable Open Source RTOS
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arch.h
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1/*
2 * Copyright (c) 2010-2014 Wind River Systems, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
15#ifndef ZEPHYR_INCLUDE_ARCH_X86_IA32_ARCH_H_
16#define ZEPHYR_INCLUDE_ARCH_X86_IA32_ARCH_H_
17
18#include "sys_io.h"
19#include <stdbool.h>
22#include <zephyr/sys/util.h>
27
28#ifndef _ASMLANGUAGE
29#include <stddef.h> /* for size_t */
30
33#include <zephyr/pm/pm.h>
34
35#endif /* _ASMLANGUAGE */
36
37/* GDT layout */
38#define CODE_SEG 0x08
39#define DATA_SEG 0x10
40#define MAIN_TSS 0x18
41#define DF_TSS 0x20
42
43/*
44 * Use for thread local storage.
45 * Match these to gen_gdt.py.
46 * The 0x03 is added to limit privilege.
47 */
48#if defined(CONFIG_USERSPACE)
49#define GS_TLS_SEG (0x38 | 0x03)
50#elif defined(CONFIG_X86_STACK_PROTECTION)
51#define GS_TLS_SEG (0x28 | 0x03)
52#else
53#define GS_TLS_SEG (0x18 | 0x03)
54#endif
55
60#define MK_ISR_NAME(x) __isr__##x
61
62#define Z_DYN_STUB_SIZE 4
63#define Z_DYN_STUB_OFFSET 0
64#define Z_DYN_STUB_LONG_JMP_EXTRA_SIZE 3
65#define Z_DYN_STUB_PER_BLOCK 32
66
67
68#ifndef _ASMLANGUAGE
69
70#ifdef __cplusplus
71extern "C" {
72#endif
73
74/* interrupt/exception/error related definitions */
75
76typedef struct s_isrList {
78 void *fnc;
83 unsigned int irq;
85 unsigned int priority;
89 unsigned int vec;
91 unsigned int dpl;
92
97 unsigned int tss;
99
100
122#define NANO_CPU_INT_REGISTER(r, n, p, v, d) \
123 static ISR_LIST __attribute__((section(".intList"))) \
124 __attribute__((used)) MK_ISR_NAME(r) = \
125 { \
126 .fnc = &(r), \
127 .irq = (n), \
128 .priority = (p), \
129 .vec = (v), \
130 .dpl = (d), \
131 .tss = 0 \
132 }
133
147#define _X86_IDT_TSS_REGISTER(tss_p, irq_p, priority_p, vec_p, dpl_p) \
148 static ISR_LIST __attribute__((section(".intList"))) \
149 __attribute__((used)) MK_ISR_NAME(vec_p) = \
150 { \
151 .fnc = NULL, \
152 .irq = (irq_p), \
153 .priority = (priority_p), \
154 .vec = (vec_p), \
155 .dpl = (dpl_p), \
156 .tss = (tss_p) \
157 }
158
173#define _VECTOR_ARG(irq_p) (-1)
174
175#ifdef CONFIG_LINKER_USE_PINNED_SECTION
176#define IRQSTUBS_TEXT_SECTION ".pinned_text.irqstubs"
177#else
178#define IRQSTUBS_TEXT_SECTION ".text.irqstubs"
179#endif
180
181/* Internally this function does a few things:
182 *
183 * 1. There is a declaration of the interrupt parameters in the .intList
184 * section, used by gen_idt to create the IDT. This does the same thing
185 * as the NANO_CPU_INT_REGISTER() macro, but is done in assembly as we
186 * need to populate the .fnc member with the address of the assembly
187 * IRQ stub that we generate immediately afterwards.
188 *
189 * 2. The IRQ stub itself is declared. The code will go in its own named
190 * section .text.irqstubs section (which eventually gets linked into 'text')
191 * and the stub shall be named (isr_name)_irq(irq_line)_stub
192 *
193 * 3. The IRQ stub pushes the ISR routine and its argument onto the stack
194 * and then jumps to the common interrupt handling code in _interrupt_enter().
195 *
196 * 4. z_irq_controller_irq_config() is called at runtime to set the mapping
197 * between the vector and the IRQ line as well as triggering flags
198 */
199#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
200{ \
201 __asm__ __volatile__( \
202 ".pushsection .intList\n\t" \
203 ".long %c[isr]_irq%c[irq]_stub\n\t" /* ISR_LIST.fnc */ \
204 ".long %c[irq]\n\t" /* ISR_LIST.irq */ \
205 ".long %c[priority]\n\t" /* ISR_LIST.priority */ \
206 ".long %c[vector]\n\t" /* ISR_LIST.vec */ \
207 ".long 0\n\t" /* ISR_LIST.dpl */ \
208 ".long 0\n\t" /* ISR_LIST.tss */ \
209 ".popsection\n\t" \
210 ".pushsection " IRQSTUBS_TEXT_SECTION "\n\t" \
211 ".global %c[isr]_irq%c[irq]_stub\n\t" \
212 "%c[isr]_irq%c[irq]_stub:\n\t" \
213 "pushl %[isr_param]\n\t" \
214 "pushl %[isr]\n\t" \
215 "jmp _interrupt_enter\n\t" \
216 ".popsection\n\t" \
217 : \
218 : [isr] "i" (isr_p), \
219 [isr_param] "i" (isr_param_p), \
220 [priority] "i" (priority_p), \
221 [vector] "i" _VECTOR_ARG(irq_p), \
222 [irq] "i" (irq_p)); \
223 z_irq_controller_irq_config(Z_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), \
224 (flags_p)); \
225}
226
227#ifdef CONFIG_PCIE
228
229#define ARCH_PCIE_IRQ_CONNECT(bdf_p, irq_p, priority_p, \
230 isr_p, isr_param_p, flags_p) \
231 ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p)
232
233#endif /* CONFIG_PCIE */
234
235/* Direct interrupts won't work as expected with KPTI turned on, because
236 * all non-user accessible pages in the page table are marked non-present.
237 * It's likely possible to add logic to ARCH_ISR_DIRECT_HEADER/FOOTER to do
238 * the necessary trampolining to switch page tables / stacks, but this
239 * probably loses all the latency benefits that direct interrupts provide
240 * and one might as well use a regular interrupt anyway.
241 */
242#ifndef CONFIG_X86_KPTI
243#define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \
244{ \
245 NANO_CPU_INT_REGISTER(isr_p, irq_p, priority_p, -1, 0); \
246 z_irq_controller_irq_config(Z_IRQ_TO_INTERRUPT_VECTOR(irq_p), (irq_p), \
247 (flags_p)); \
248}
249
250#ifdef CONFIG_PM
251static inline void arch_irq_direct_pm(void)
252{
253 if (_kernel.idle) {
254 _kernel.idle = 0;
256 }
257}
258
259#define ARCH_ISR_DIRECT_PM() arch_irq_direct_pm()
260#else
261#define ARCH_ISR_DIRECT_PM() do { } while (false)
262#endif
263
264#define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header()
265#define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap)
266
267/* FIXME:
268 * tracing/tracing.h cannot be included here due to circular dependency
269 */
270#if defined(CONFIG_TRACING)
271void sys_trace_isr_enter(void);
272void sys_trace_isr_exit(void);
273#endif
274
275static inline void arch_isr_direct_header(void)
276{
277#if defined(CONFIG_TRACING)
279#endif
280
281 /* We're not going to unlock IRQs, but we still need to increment this
282 * so that arch_is_in_isr() works
283 */
284 ++_kernel.cpus[0].nested;
285}
286
287/*
288 * FIXME: z_swap_irqlock is an inline function declared in a private header and
289 * cannot be referenced from a public header, so we move it to an
290 * external function.
291 */
292void arch_isr_direct_footer_swap(unsigned int key);
293
294static inline void arch_isr_direct_footer(int swap)
295{
296 z_irq_controller_eoi();
297#if defined(CONFIG_TRACING)
299#endif
300 --_kernel.cpus[0].nested;
301
302 /* Call swap if all the following is true:
303 *
304 * 1) swap argument was enabled to this function
305 * 2) We are not in a nested interrupt
306 * 3) Next thread to run in the ready queue is not this thread
307 */
308 if (swap != 0 && _kernel.cpus[0].nested == 0 &&
309 _kernel.ready_q.cache != _current) {
310 unsigned int flags;
311
312 /* Fetch EFLAGS argument to z_swap() */
313 __asm__ volatile (
314 "pushfl\n\t"
315 "popl %0\n\t"
316 : "=g" (flags)
317 :
318 : "memory"
319 );
320
322 }
323}
324
325#define ARCH_ISR_DIRECT_DECLARE(name) \
326 static inline int name##_body(void); \
327 __attribute__ ((interrupt)) void name(void *stack_frame) \
328 { \
329 ARG_UNUSED(stack_frame); \
330 int check_reschedule; \
331 ISR_DIRECT_HEADER(); \
332 check_reschedule = name##_body(); \
333 ISR_DIRECT_FOOTER(check_reschedule); \
334 } \
335 static inline int name##_body(void)
336#endif /* !CONFIG_X86_KPTI */
337
338static ALWAYS_INLINE unsigned int arch_irq_lock(void)
339{
340 unsigned int key;
341
342 __asm__ volatile ("pushfl; cli; popl %0" : "=g" (key) :: "memory");
343
344 return key;
345}
346
347
353#define NANO_SOFT_IRQ ((unsigned int) (-1))
354
355#ifdef CONFIG_X86_ENABLE_TSS
356extern struct task_state_segment _main_tss;
357#endif
358
359#define ARCH_EXCEPT(reason_p) do { \
360 __asm__ volatile( \
361 "push %[reason]\n\t" \
362 "int %[vector]\n\t" \
363 : \
364 : [vector] "i" (Z_X86_OOPS_VECTOR), \
365 [reason] "i" (reason_p)); \
366 CODE_UNREACHABLE; /* LCOV_EXCL_LINE */ \
367} while (false)
368
369/*
370 * Dynamic thread object memory alignment.
371 *
372 * If support for SSEx extensions is enabled a 16 byte boundary is required,
373 * since the 'fxsave' and 'fxrstor' instructions require this. In all other
374 * cases a 4 byte boundary is sufficient.
375 */
376#if defined(CONFIG_EAGER_FPU_SHARING) || defined(CONFIG_LAZY_FPU_SHARING)
377#ifdef CONFIG_SSE
378#define ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT 16
379#else
380#define ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT (sizeof(void *))
381#endif
382#else
383/* No special alignment requirements, simply align on pointer size. */
384#define ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT (sizeof(void *))
385#endif /* CONFIG_*_FP_SHARING */
386
387
388#ifdef __cplusplus
389}
390#endif
391
392#endif /* !_ASMLANGUAGE */
393
394#endif /* ZEPHYR_INCLUDE_ARCH_X86_IA32_ARCH_H_ */
IA-32 specific gdbstub interface header.
x86 (IA32) specific syscall header
Per-arch thread definition.
void pm_system_resume(void)
Notify exit from kernel sleep.
void sys_trace_isr_enter(void)
Called when entering an ISR.
void sys_trace_isr_exit(void)
Called when exiting an ISR.
#define ALWAYS_INLINE
Definition common.h:160
static ALWAYS_INLINE unsigned int arch_irq_lock(void)
Definition arch.h:72
flags
Definition parser.h:97
Definition arch.h:76
unsigned int tss
If nonzero, specifies a TSS segment selector.
Definition arch.h:97
void * fnc
Address of ISR/stub.
Definition arch.h:78
unsigned int dpl
Privilege level associated with ISR/stub.
Definition arch.h:91
unsigned int irq
IRQ associated with the ISR/stub, or -1 if this is not associated with a real interrupt; in this case...
Definition arch.h:83
unsigned int vec
Vector number associated with ISR/stub, or -1 to assign based on priority.
Definition arch.h:89
unsigned int priority
Priority associated with the IRQ.
Definition arch.h:85
Definition segmentation.h:54
Misc utilities.
static void arch_isr_direct_footer(int swap)
Definition arch.h:294
void arch_isr_direct_footer_swap(unsigned int key)
struct s_isrList ISR_LIST
static void arch_isr_direct_header(void)
Definition arch.h:275