IA-32 specific kernel interface header This header contains the IA-32 specific kernel interface.
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#define | CODE_SEG 0x08 |
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#define | DATA_SEG 0x10 |
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#define | MAIN_TSS 0x18 |
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#define | DF_TSS 0x20 |
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#define | GS_TLS_SEG (0x38 | 0x03) |
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#define | MK_ISR_NAME(x) __isr__##x |
| Macro used internally by NANO_CPU_INT_REGISTER and NANO_CPU_INT_REGISTER_ASM.
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#define | NANO_CPU_INT_REGISTER(r, n, p, v, d) |
| Connect a routine to an interrupt vector.
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#define | IRQSTUBS_TEXT_SECTION ".text.irqstubs" |
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#define | ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) |
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#define | ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) |
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#define | ARCH_ISR_DIRECT_PM() do { } while (false) |
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#define | ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header() |
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#define | ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap) |
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#define | ARCH_ISR_DIRECT_DECLARE(name) |
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#define | NANO_SOFT_IRQ ((unsigned int) (-1)) |
| The NANO_SOFT_IRQ macro must be used as the value for the irq parameter to NANO_CPU_INT_REGISTER when connecting to an interrupt that does not correspond to any IRQ line (such as spurious vector or SW IRQ)
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#define | ARCH_EXCEPT(reason_p) |
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#define | ARCH_DYNAMIC_OBJ_K_THREAD_ALIGNMENT (sizeof(void *)) |
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IA-32 specific kernel interface header This header contains the IA-32 specific kernel interface.
It is included by the generic kernel interface header (include/arch/cpu.h)
#define NANO_CPU_INT_REGISTER |
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r, |
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n, |
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p, |
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v, |
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Value: static ISR_LIST __attribute__((section(
".intList"))) \
{ \
.irq = (n), \
.priority = (p), \
.vec = (v), \
.tss = 0 \
}
irp nz macro MOVR cc d
Definition asm-macro-32-bit-gnu.h:11
workaround assembler barfing for ST r
Definition asm-macro-32-bit-gnu.h:24
void * fnc
Address of ISR/stub.
Definition arch.h:77
#define MK_ISR_NAME(x)
Macro used internally by NANO_CPU_INT_REGISTER and NANO_CPU_INT_REGISTER_ASM.
Definition arch.h:59
Connect a routine to an interrupt vector.
This macro "connects" the specified routine, r, to the specified interrupt vector, v using the descriptor privilege level d. On the IA-32 architecture, an interrupt vector is a value from 0 to 255. This macro populates the special intList section with the address of the routine, the vector number and the descriptor privilege level. The genIdt tool then picks up this information and generates an actual IDT entry with this information properly encoded.
The d argument specifies the privilege level for the interrupt-gate descriptor; (hardware) interrupts and exceptions should specify a level of 0, whereas handlers for user-mode software generated interrupts should specify 3.
- Parameters
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r | Routine to be connected |
n | IRQ number |
p | IRQ priority |
v | Interrupt Vector |
d | Descriptor Privilege Level |