Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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arch.h
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1/*
2 * Copyright (c) 2016 Cadence Design Systems, Inc.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
13#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_H_
14#define ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_H_
15
16#include <zephyr/irq.h>
17
18#include <zephyr/devicetree.h>
19#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
20#include <zephyr/types.h>
21#include <zephyr/toolchain.h>
25#include <zephyr/sw_isr_table.h>
29#include <xtensa/config/core.h>
32#include <zephyr/debug/sparse.h>
34#include <zephyr/sys/slist.h>
35
37
38#ifdef CONFIG_XTENSA_MMU
40#endif
41
42#ifdef CONFIG_XTENSA_MPU
44#endif
45
58
59#ifdef __cplusplus
60extern "C" {
61#endif
62
63struct arch_mem_domain {
64#ifdef CONFIG_XTENSA_MMU
65 uint32_t *ptables __aligned(CONFIG_MMU_PAGE_SIZE);
66 uint8_t asid;
67 bool dirty;
68#endif
69#ifdef CONFIG_XTENSA_MPU
70 struct xtensa_mpu_map mpu_map;
71#endif
73};
74
82void xtensa_arch_except(int reason_p);
83
92void xtensa_arch_kernel_oops(int reason_p, void *ssf);
93
94#ifdef CONFIG_USERSPACE
95
96#define ARCH_EXCEPT(reason_p) do { \
97 if (k_is_user_context()) { \
98 arch_syscall_invoke1(reason_p, \
99 K_SYSCALL_XTENSA_USER_FAULT); \
100 } else { \
101 xtensa_arch_except(reason_p); \
102 } \
103 CODE_UNREACHABLE; \
104} while (false)
105
106#else
107
108#define ARCH_EXCEPT(reason_p) do { \
109 xtensa_arch_except(reason_p); \
110 CODE_UNREACHABLE; \
111 } while (false)
112
113#endif
114
115__syscall void xtensa_user_fault(unsigned int reason);
116
117#include <zephyr/syscalls/arch.h>
118
119/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
120void z_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags);
121
122#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
123 { \
124 Z_ISR_DECLARE(irq_p, flags_p, isr_p, isr_param_p); \
125 }
126
128static inline uint32_t arch_k_cycle_get_32(void)
129{
130 return sys_clock_cycle_get_32();
131}
132
134static inline uint64_t arch_k_cycle_get_64(void)
135{
136 return sys_clock_cycle_get_64();
137}
138
140static ALWAYS_INLINE void arch_nop(void)
141{
142 __asm__ volatile("nop");
143}
144
154{
155 int vecbase;
156
157 __asm__ volatile("rsr.vecbase %0" : "=r" (vecbase));
158 __asm__ volatile("wsr.vecbase %0; rsync" : : "r" (vecbase | 1));
159}
160
161#if defined(CONFIG_XTENSA_RPO_CACHE) || defined(__DOXYGEN__)
162#if defined(CONFIG_ARCH_HAS_COHERENCE) || defined(__DOXYGEN__)
164static inline bool arch_mem_coherent(void *ptr)
165{
166 size_t addr = (size_t) ptr;
167
168 return (addr >> 29) == CONFIG_XTENSA_UNCACHED_REGION;
169}
170#endif
171
172
173/* Utility to generate an unrolled and optimal[1] code sequence to set
174 * the RPO TLB registers (contra the HAL cacheattr macros, which
175 * generate larger code and can't be called from C), based on the
176 * KERNEL_COHERENCE configuration in use. Selects RPO attribute "2"
177 * for regions (including MMIO registers in region zero) which want to
178 * bypass L1, "4" for the cached region which wants writeback, and
179 * "15" (invalid) elsewhere.
180 *
181 * Note that on cores that have the "translation" option set, we need
182 * to put an identity mapping in the high bits. Also per spec
183 * changing the current code region (by definition cached) requires
184 * that WITLB be followed by an ISYNC and that both instructions live
185 * in the same cache line (two 3-byte instructions fit in an 8-byte
186 * aligned region, so that's guaranteed not to cross a cache line
187 * boundary).
188 *
189 * [1] With the sole exception of gcc's infuriating insistence on
190 * emitting a precomputed literal for addr + addrincr instead of
191 * computing it with a single ADD instruction from values it already
192 * has in registers. Explicitly assigning the variables to registers
193 * via an attribute works, but then emits needless MOV instructions
194 * instead. I tell myself it's just 32 bytes of .text, but... Sigh.
195 */
196#define _REGION_ATTR(r) \
197 ((r) == 0 ? 2 : \
198 ((r) == CONFIG_XTENSA_CACHED_REGION ? 4 : \
199 ((r) == CONFIG_XTENSA_UNCACHED_REGION ? 2 : 15)))
200
201#define _SET_ONE_TLB(region) do { \
202 uint32_t attr = _REGION_ATTR(region); \
203 if (XCHAL_HAVE_XLT_CACHEATTR) { \
204 attr |= addr; /* RPO with translation */ \
205 } \
206 if (region != CONFIG_XTENSA_CACHED_REGION) { \
207 __asm__ volatile("wdtlb %0, %1; witlb %0, %1" \
208 :: "r"(attr), "r"(addr)); \
209 } else { \
210 __asm__ volatile("wdtlb %0, %1" \
211 :: "r"(attr), "r"(addr)); \
212 __asm__ volatile("j 1f; .align 8; 1:"); \
213 __asm__ volatile("witlb %0, %1; isync" \
214 :: "r"(attr), "r"(addr)); \
215 } \
216 addr += addrincr; \
217} while (0)
218
222#define ARCH_XTENSA_SET_RPO_TLB() \
223 do { \
224 register uint32_t addr = 0, addrincr = 0x20000000; \
225 FOR_EACH(_SET_ONE_TLB, (;), 0, 1, 2, 3, 4, 5, 6, 7); \
226 } while (0)
227#endif /* CONFIG_XTENSA_RPO_CACHE */
228
229#if defined(CONFIG_XTENSA_MMU) || defined(__DOXYGEN__)
240void arch_xtensa_mmu_post_init(bool is_core0);
241#endif
242
243#ifdef __cplusplus
244}
245#endif
246
247#endif /* !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) */
248
249#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_H_ */
static ALWAYS_INLINE void arch_nop(void)
Definition arch.h:348
Xtensa specific syscall header.
#define ALWAYS_INLINE
Definition common.h:129
Devicetree main header.
struct _snode sys_snode_t
Single-linked list node structure.
Definition slist.h:39
Public interface for configuring interrupts.
uint64_t sys_clock_cycle_get_64(void)
uint32_t sys_clock_cycle_get_32(void)
static uint32_t arch_k_cycle_get_32(void)
Definition arch.h:99
static uint64_t arch_k_cycle_get_64(void)
Definition arch.h:106
flags
Definition parser.h:96
void * ptr
Definition printk.c:177
Size of off_t must be equal or less than size of size_t
Definition retained_mem.h:28
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
__UINT64_TYPE__ uint64_t
Definition stdint.h:91
__UINT8_TYPE__ uint8_t
Definition stdint.h:88
Definition arch.h:46
sys_snode_t node
Definition arch.h:50
pentry_t * ptables
Definition mmustructs.h:75
Struct to hold foreground MPU map and its entries.
Definition mpu.h:186
Software-managed ISR table.
Timer driver API.
Macros to abstract toolchain specific capabilities.
void xtensa_user_fault(unsigned int reason)
void xtensa_arch_kernel_oops(int reason_p, void *ssf)
Generate kernel oops.
void xtensa_arch_except(int reason_p)
Generate hardware exception.
static bool arch_mem_coherent(void *ptr)
Implementation of arch_mem_coherent.
Definition arch.h:164
void arch_xtensa_mmu_post_init(bool is_core0)
Perform additional steps after MMU initialization.
static ALWAYS_INLINE void xtensa_vecbase_lock(void)
Lock VECBASE if supported by hardware.
Definition arch.h:153
Xtensa public exception handling.