Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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arch.h File Reference

Xtensa specific kernel interface header This header contains the Xtensa specific kernel interface. More...

Go to the source code of this file.

Data Structures

struct  arch_mem_domain
 

Macros

#define ARCH_EXCEPT(reason_p)
 
#define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p)
 
#define ARCH_XTENSA_SET_RPO_TLB()
 Setup RPO TLB registers.
 

Functions

void xtensa_arch_except (int reason_p)
 Generate hardware exception.
 
void xtensa_arch_kernel_oops (int reason_p, void *ssf)
 Generate kernel oops.
 
void xtensa_user_fault (unsigned int reason)
 
static uint32_t arch_k_cycle_get_32 (void)
 Implementation of arch_k_cycle_get_32.
 
static uint64_t arch_k_cycle_get_64 (void)
 Implementation of arch_k_cycle_get_64.
 
static ALWAYS_INLINE void arch_nop (void)
 Implementation of arch_nop.
 
static ALWAYS_INLINE void xtensa_vecbase_lock (void)
 Lock VECBASE if supported by hardware.
 
static bool arch_mem_coherent (void *ptr)
 Implementation of arch_mem_coherent.
 
void arch_xtensa_mmu_post_init (bool is_core0)
 Perform additional steps after MMU initialization.
 

Detailed Description

Xtensa specific kernel interface header This header contains the Xtensa specific kernel interface.

It is included by the generic kernel interface header (include/zephyr/arch/cpu.h)

Macro Definition Documentation

◆ ARCH_EXCEPT

#define ARCH_EXCEPT (   reason_p)
Value:
do { \
if (k_is_user_context()) { \
arch_syscall_invoke1(reason_p, \
K_SYSCALL_XTENSA_USER_FAULT); \
} else { \
xtensa_arch_except(reason_p); \
} \
CODE_UNREACHABLE; \
} while (false)
static __pinned_func bool k_is_user_context(void)
Indicate whether the CPU is currently in user mode.
Definition syscall.h:115

◆ ARCH_IRQ_CONNECT

#define ARCH_IRQ_CONNECT (   irq_p,
  priority_p,
  isr_p,
  isr_param_p,
  flags_p 
)
Value:
{ \
Z_ISR_DECLARE(irq_p, flags_p, isr_p, isr_param_p); \
}

◆ ARCH_XTENSA_SET_RPO_TLB

#define ARCH_XTENSA_SET_RPO_TLB ( )
Value:
do { \
register uint32_t addr = 0, addrincr = 0x20000000; \
FOR_EACH(_SET_ONE_TLB, (;), 0, 1, 2, 3, 4, 5, 6, 7); \
} while (0)
__UINT32_TYPE__ uint32_t
Definition stdint.h:90

Setup RPO TLB registers.

Function Documentation

◆ arch_k_cycle_get_32()

static uint32_t arch_k_cycle_get_32 ( void  )
inlinestatic

Implementation of arch_k_cycle_get_32.

◆ arch_k_cycle_get_64()

static uint64_t arch_k_cycle_get_64 ( void  )
inlinestatic

Implementation of arch_k_cycle_get_64.

◆ arch_mem_coherent()

static bool arch_mem_coherent ( void *  ptr)
inlinestatic

Implementation of arch_mem_coherent.

◆ arch_nop()

static ALWAYS_INLINE void arch_nop ( void  )
static

Implementation of arch_nop.

◆ arch_xtensa_mmu_post_init()

void arch_xtensa_mmu_post_init ( bool  is_core0)

Perform additional steps after MMU initialization.

This performs additional steps related to memory management after the main MMU initialization code. This needs to defined in the SoC layer. Default is do no nothing.

Parameters
is_core0True if this is called while executing on CPU core #0.

◆ xtensa_arch_except()

void xtensa_arch_except ( int  reason_p)

Generate hardware exception.

This generates hardware exception which is used by ARCH_EXCEPT().

Parameters
reason_pReason for exception.

◆ xtensa_arch_kernel_oops()

void xtensa_arch_kernel_oops ( int  reason_p,
void *  ssf 
)

Generate kernel oops.

This generates kernel oops which is used by arch_syscall_oops().

Parameters
reason_pReason for exception.
ssfStack pointer.

◆ xtensa_user_fault()

void xtensa_user_fault ( unsigned int  reason)

◆ xtensa_vecbase_lock()

static ALWAYS_INLINE void xtensa_vecbase_lock ( void  )
static

Lock VECBASE if supported by hardware.

The bit 0 of VECBASE acts as a lock bit on hardware supporting this feature. When this bit is set, VECBASE cannot be changed until it is cleared by hardware reset. When the hardware does not support this bit, it is hardwired to 0.