Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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arch_inlines.h
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1/*
2 * Copyright (c) 2016 Cadence Design Systems, Inc.
3 * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_
9#define ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_
10
11#ifndef _ASMLANGUAGE
12
14#include <zephyr/zsr.h>
15
23#define XTENSA_RSR(sr) \
24 ({uint32_t v; \
25 __asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
26 v; })
27
34#define XTENSA_WSR(sr, v) \
35 do { \
36 __asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
37 } while (false)
38
46#define XTENSA_RUR(ur) \
47 ({uint32_t v; \
48 __asm__ volatile ("rur." ur " %0" : "=a"(v)); \
49 v; })
50
57#define XTENSA_WUR(ur, v) \
58 do { \
59 __asm__ volatile ("wur." ur " %0" : : "r"(v)); \
60 } while (false)
61
63static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
64{
65 _cpu_t *cpu;
66
67 cpu = (_cpu_t *)XTENSA_RSR(ZSR_CPU_STR);
68
69 return cpu;
70}
71
74{
75 uint32_t prid;
76
77 __asm__ volatile("rsr %0, PRID" : "=r"(prid));
78 return prid;
79}
80
81#ifdef CONFIG_SOC_HAS_RUNTIME_NUM_CPUS
82extern unsigned int soc_num_cpus;
83#endif
84
86static ALWAYS_INLINE unsigned int arch_num_cpus(void)
87{
88#ifdef CONFIG_SOC_HAS_RUNTIME_NUM_CPUS
89 return soc_num_cpus;
90#else
91 return CONFIG_MP_MAX_NUM_CPUS;
92#endif
93}
94
95#endif /* !_ASMLANGUAGE */
96
97#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_ */
static ALWAYS_INLINE _cpu_t * arch_curr_cpu(void)
Definition arch_inlines.h:17
static ALWAYS_INLINE uint32_t arch_proc_id(void)
Definition arch_inlines.h:30
static ALWAYS_INLINE unsigned int arch_num_cpus(void)
Definition arch_inlines.h:39
#define ALWAYS_INLINE
Definition common.h:129
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
#define XTENSA_RSR(sr)
Read a special register.
Definition arch_inlines.h:23