Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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arch_inlines.h File Reference
#include <zephyr/kernel_structs.h>
#include <zephyr/zsr.h>

Go to the source code of this file.

Macros

#define XTENSA_RSR(sr)
 Read a special register.
 
#define XTENSA_WSR(sr, v)
 Write to a special register.
 
#define XTENSA_RUR(ur)
 Read a user register.
 
#define XTENSA_WUR(ur, v)
 Write to a user register.
 

Functions

static ALWAYS_INLINE _cpu_t * arch_curr_cpu (void)
 Implementation of arch_curr_cpu.
 
static ALWAYS_INLINE uint32_t arch_proc_id (void)
 Implementation of arch_proc_id.
 
static ALWAYS_INLINE unsigned int arch_num_cpus (void)
 Implementation of arch_num_cpus.
 

Macro Definition Documentation

◆ XTENSA_RSR

#define XTENSA_RSR (   sr)
Value:
({uint32_t v; \
__asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
v; })
__UINT32_TYPE__ uint32_t
Definition stdint.h:90

Read a special register.

Parameters
srName of special register.
Returns
Value of special register.

◆ XTENSA_RUR

#define XTENSA_RUR (   ur)
Value:
({uint32_t v; \
__asm__ volatile ("rur." ur " %0" : "=a"(v)); \
v; })

Read a user register.

Parameters
urName of user register.
Returns
Value of user register.

◆ XTENSA_WSR

#define XTENSA_WSR (   sr,
 
)
Value:
do { \
__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
} while (false)

Write to a special register.

Parameters
srName of special register.
vValue to be written to special register.

◆ XTENSA_WUR

#define XTENSA_WUR (   ur,
 
)
Value:
do { \
__asm__ volatile ("wur." ur " %0" : : "r"(v)); \
} while (false)

Write to a user register.

Parameters
urName of user register.
vValue to be written to user register.

Function Documentation

◆ arch_curr_cpu()

static ALWAYS_INLINE _cpu_t * arch_curr_cpu ( void  )
static

Implementation of arch_curr_cpu.

◆ arch_num_cpus()

static ALWAYS_INLINE unsigned int arch_num_cpus ( void  )
static

Implementation of arch_num_cpus.

◆ arch_proc_id()

static ALWAYS_INLINE uint32_t arch_proc_id ( void  )
static

Implementation of arch_proc_id.