Zephyr Architecture Configuration Options

Kconfig files describe build-time configuration options (called symbols in Kconfig-speak), how they’re grouped into menus and sub-menus, and dependencies between them that determine what configurations are valid.

Kconfig files appear throughout the directory tree. For example, subsys/power/Kconfig defines power-related options.

This documentation is generated automatically from the Kconfig files by the gen_kconfig_rest.py script. Click on symbols for more information.

Configuration Options

Symbol name	Help/prompt
CONFIG_64BIT	This option tells the build system that the target system is using a 64-bit address space, meaning that pointer and long types are 64 bits wide. This option is selected by arch/$ARCH/Kconfig, soc//Kconfig, or boards//Kconfig and the user should generally avoid modifying it.
CONFIG_AARCH64_IMAGE_HEADER	This option enables standard ARM64 boot image header used by Linux and understood by loaders such as u-boot on Xen xl tool.
CONFIG_ACPI	Allow retrieval of platform configuration at runtime.
CONFIG_ARC	ARC architecture
CONFIG_ARCH	System architecture string.
CONFIG_ARCH_HAS_COHERENCE	When selected, the architecture supports the arch_mem_coherent() API and can link into incoherent/cached memory using the “.cached” linker section.
CONFIG_ARCH_HAS_DEMAND_PAGING	This hidden configuration should be selected by the architecture if demand paging is supported.
CONFIG_ARCH_HAS_EXECUTABLE_PAGE_BIT
CONFIG_ARCH_HAS_EXTRA_EXCEPTION_INFO
CONFIG_ARCH_HAS_GDBSTUB
CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION
CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT
CONFIG_ARCH_HAS_RAMFUNC_SUPPORT
CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES	This hidden configuration should be selected by the architecture if certain RAM page frames need to be marked as reserved and never used for memory mappings. The architecture will need to implement arch_reserved_pages_update().
CONFIG_ARCH_HAS_STACK_PROTECTION
CONFIG_ARCH_HAS_THREAD_ABORT
CONFIG_ARCH_HAS_THREAD_LOCAL_STORAGE
CONFIG_ARCH_HAS_TIMING_FUNCTIONS
CONFIG_ARCH_HAS_TRUSTED_EXECUTION
CONFIG_ARCH_HAS_USERSPACE
CONFIG_ARCH_IS_SET	Helper symbol to detect SoCs forgetting to select one of the arch symbols above. See the top-level CMakeLists.txt.
CONFIG_ARCH_MAPS_ALL_RAM	This hidden option is selected by the architecture to inform the kernel that all RAM is mapped at boot, and not just the bounds of the Zephyr image. If RAM starts at 0x0, the first page must remain un-mapped to catch NULL pointer dereferences. With this enabled, the kernel will not assume that virtual memory addresses past the kernel image are available for mappings, but instead takes into account an entire RAM mapping instead. This is typically set by architectures which need direct access to all memory. It is the architecture’s responsibility to mark reserved memory regions as such in arch_reserved_pages_update(). Although the kernel will not disturb this RAM mapping by re-mapping the associated virtual addresses elsewhere, this is limited to only management of the virtual address space. The kernel’s page frame ontology will not consider this mapping at all; non-kernel pages will be considered free (unless marked as reserved) and Z_PAGE_FRAME_MAPPED will not be set.
CONFIG_ARCH_POSIX	POSIX (native) architecture
CONFIG_ARCH_POSIX_RECOMMENDED_STACK_SIZE	In bytes, stack size for Zephyr threads meant only for the POSIX architecture. (In this architecture only part of the thread status is kept in the Zephyr thread stack, the real stack is the native underlying pthread stack. Therefore the allocated stack can be limited to this size)
CONFIG_ARCH_SUPPORTS_ARCH_HW_INIT
CONFIG_ARCH_SUPPORTS_COREDUMP
CONFIG_ARCH_SW_ISR_TABLE_ALIGN	This option controls alignment size of generated _sw_isr_table. Some architecture needs a software ISR table to be aligned to architecture specific size. The default size is 0 for no alignment.
CONFIG_ARC_CONNECT	ARC is configured with ARC CONNECT which is a hardware for connecting multi cores.
CONFIG_ARC_CORE_MPU	ARC core MPU functionalities
CONFIG_ARC_EXCEPTION_DEBUG	Print human-readable information about exception vectors, cause codes, and parameters, at a cost of code/data size for the human-readable strings.
CONFIG_ARC_EXCEPTION_STACK_SIZE	Size in bytes of exception handling stack which is at the top of interrupt stack to get smaller memory footprint because exception is not frequent. To reduce the impact on interrupt handling, especially nested interrupt, it cannot be too large.
CONFIG_ARC_FIRQ	Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts with highest priority, status32 and pc will be saved in aux regs, other regs will be saved according to the number of register bank; If FIRQ is disabled, the handle of interrupts with highest priority will be same with other interrupts.
CONFIG_ARC_FIRQ_STACK	Use separate stack for FIRQ handing. When the fast irq is also a direct irq, this will get the minimal interrupt latency.
CONFIG_ARC_FIRQ_STACK_SIZE	The size of firq stack.
CONFIG_ARC_HAS_ACCL_REGS	Depending on the configuration, CPU can contain accumulator reg-pair (also referred to as r58:r59). These can also be used by gcc as GPR so kernel needs to save/restore per process
CONFIG_ARC_HAS_SECURE	This option is enabled when ARC core supports secure mode
CONFIG_ARC_HAS_STACK_CHECKING	ARC is configured with STACK_CHECKING which is a mechanism for checking stack accesses and raising an exception when a stack overflow or underflow is detected.
CONFIG_ARC_MPU	Target has ARC MPU (currently only works for EMSK 2.2/2.3 ARCEM7D)
CONFIG_ARC_MPU_ENABLE	Enable MPU
CONFIG_ARC_MPU_VER	ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes; For MPU v3, the minimum region is 32 bytes
CONFIG_ARC_NORMAL_FIRMWARE	This option indicates that we are building a Zephyr image that is intended to execute in normal mode. Execution of this image is triggered by secure firmware that executes in secure mode. The option is only applicable to ARC processors that implement the SecureShield. This option enables Zephyr to include code that executes in normal mode only, as well as to exclude code that is designed to execute only in secure mode. Code executing in normal mode has no access to secure resources of the ARC processors, and, therefore, it shall avoid accessing them.
CONFIG_ARC_SECURE_FIRMWARE	This option indicates that we are building a Zephyr image that is intended to execute in secure mode. The option is only applicable to ARC processors that implement the SecureShield. This option enables Zephyr to include code that executes in secure mode, as well as to exclude code that is designed to execute only in normal mode. Code executing in secure mode has access to both the secure and normal resources of the ARC processors.
CONFIG_ARC_STACK_CHECKING	Use ARC STACK_CHECKING to do stack protection
CONFIG_ARC_STACK_PROTECTION	This option enables either: - The ARC stack checking, or - the MPU-based stack guard to cause a system fatal error if the bounds of the current process stack are overflowed. The two stack guard options are mutually exclusive. The selection of the ARC stack checking is prioritized over the MPU-based stack guard.
CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS	ARC EM cores w/o secure shield 2+2 mode support might be configured to support unaligned memory access which is then disabled by default. Enable unaligned access in hardware and make software to use it.
CONFIG_ARM	ARM architecture
CONFIG_ARM64
CONFIG_ARM64_PA_BITS
CONFIG_ARM64_PA_BITS_32	32-bit
CONFIG_ARM64_PA_BITS_36	36-bit
CONFIG_ARM64_PA_BITS_42	42-bit
CONFIG_ARM64_PA_BITS_48	48-bit
CONFIG_ARM64_VA_BITS
CONFIG_ARM64_VA_BITS_32	32-bit
CONFIG_ARM64_VA_BITS_36	36-bit
CONFIG_ARM64_VA_BITS_42	42-bit
CONFIG_ARM64_VA_BITS_48	48-bit
CONFIG_ARMV6_M_ARMV8_M_BASELINE	This option signifies the use of an ARMv6-M processor implementation, or the use of an ARMv8-M processor supporting the Baseline implementation. Notes: - A Processing Element (PE) without the Main Extension is also referred to as a Baseline Implementation. A Baseline implementation has a subset of the instructions, registers, and features, of a Mainline implementation. - ARMv6-M compatibility is provided by all ARMv8-M implementations.
CONFIG_ARMV7_EXCEPTION_STACK_SIZE	This option specifies the size of the stack used by the undefined instruction and data abort exception handlers.
CONFIG_ARMV7_FIQ_STACK_SIZE	This option specifies the size of the stack used by the FIQ handler.
CONFIG_ARMV7_M_ARMV8_M_FP	This option signifies the use of an ARMv7-M processor implementation, or the use of an ARMv8-M processor implementation supporting the Floating-Point Extension.
CONFIG_ARMV7_M_ARMV8_M_MAINLINE	This option signifies the use of an ARMv7-M processor implementation, or the use of a backwards-compatible ARMv8-M processor implementation supporting the Main Extension. Notes: - A Processing Element (PE) with the Main Extension is also referred to as a Mainline Implementation. - ARMv7-M compatibility requires the Main Extension. From https://developer.arm.com/products/architecture/m-profile: The Main Extension provides backwards compatibility with ARMv7-M.
CONFIG_ARMV7_R	This option signifies the use of an ARMv7-R processor implementation. From https://developer.arm.com/products/architecture/cpu-architecture/r-profile: The Armv7-R architecture implements a traditional Arm architecture with multiple modes and supports a Protected Memory System Architecture (PMSA) based on a Memory Protection Unit (MPU). It supports the Arm (32) and Thumb (T32) instruction sets.
CONFIG_ARMV7_R_FP	This option signifies the use of an ARMv7-R processor implementation supporting the Floating-Point Extension.
CONFIG_ARMV7_SVC_STACK_SIZE	This option specifies the size of the stack used by the SVC handler.
CONFIG_ARMV7_SYS_STACK_SIZE	This option specifies the size of the stack used by the system mode.
CONFIG_ARMV8_A	This option signifies the use of an ARMv8-A processor implementation. From https://developer.arm.com/products/architecture/cpu-architecture/a-profile: The Armv8-A architecture introduces the ability to use 64-bit and 32-bit Execution states, known as AArch64 and AArch32 respectively. The AArch64 Execution state supports the A64 instruction set, holds addresses in 64-bit registers and allows instructions in the base instruction set to use 64-bit registers for their processing. The AArch32 Execution state is a 32-bit Execution state that preserves backwards compatibility with the Armv7-A architecture and enhances that profile so that it can support some features included in the AArch64 state. It supports the T32 and A32 instruction sets.
CONFIG_ARMV8_A_NS	This option signifies that Zephyr is entered in TrustZone Non-Secure state
CONFIG_ARMV8_M_BASELINE	This option signifies the use of an ARMv8-M processor implementation. ARMv8-M Baseline includes additional features not present in the ARMv6-M architecture.
CONFIG_ARMV8_M_DSP	This option signifies the use of an ARMv8-M processor implementation supporting the DSP Extension.
CONFIG_ARMV8_M_MAINLINE	This option signifies the use of an ARMv8-M processor implementation, supporting the Main Extension. ARMv8-M Main Extension includes additional features not present in the ARMv7-M architecture.
CONFIG_ARMV8_M_SE	This option signifies the use of an ARMv8-M processor implementation (Baseline or Mainline) supporting the Security Extensions.
CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER	This option indicates that the ARM CPU is connected to a custom (i.e. non-GIC) interrupt controller. A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, …) allow interfacing to a custom external interrupt controller and this option must be selected when such cores are connected to an interrupt controller that is not the ARM Generic Interrupt Controller (GIC). When this option is selected, the architecture interrupt control functions are mapped to the SoC interrupt control interface, which is implemented at the SoC level. N.B. This option is only applicable to the Cortex-A and Cortex-R family cores. The Cortex-M family cores are always equipped with the ARM Nested Vectored Interrupt Controller (NVIC).
CONFIG_ARM_ENTRY_VENEERS_LIB_NAME	Library file to find the symbol table for the entry veneers. The library will typically come from building the Secure Firmware that contains secure entry functions, and allows the Non-Secure Firmware to call into the Secure Firmware.
CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS	Option indicates that ARM Secure Firmware contains Secure Entry functions that may be called from Non-Secure state. Secure Entry functions must be located in Non-Secure Callable memory regions.
CONFIG_ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS	Option indicates that ARM Non-Secure Firmware uses Secure Entry functions provided by the Secure Firmware. The Secure Firmware must be configured to provide these functions.
CONFIG_ARM_MMU	Memory Management Unit support.
CONFIG_ARM_MPU	MCU implements Memory Protection Unit. Notes: The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two alignment of MPU region base address and size. The NXP MPU as well as the ARMv8-M MPU do not require MPU regions to have power-of-two alignment for base address and region size. The ARMv8-M MPU requires the active MPU regions be non-overlapping. As a result of this, the ARMv8-M MPU needs to fully partition the memory map when programming dynamic memory regions (e.g. PRIV stack guard, user thread stack, and application memory domains), if the system requires PRIV access policy different from the access policy of the ARMv8-M background memory map. The application developer may enforce full PRIV (kernel) memory partition by enabling the CONFIG_MPU_GAP_FILLING option. By not enforcing full partition, MPU may leave part of kernel SRAM area covered only by the default ARMv8-M memory map. This is fine for User Mode, since the background ARM map does not allow nPRIV access at all. However, since the background map policy allows instruction fetches by privileged code, forcing this Kconfig option off prevents the system from directly triggering MemManage exceptions upon accidental attempts to execute code from SRAM in XIP builds. Since this does not compromise User Mode, we make the skipping of full partitioning the default behavior for the ARMv8-M MPU driver.
CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE	Minimum size (and alignment) of an ARM MPU region. Use this symbol to guarantee minimum size and alignment of MPU regions. A minimum 4-byte alignment is enforced in ARM builds without support for Memory Protection.
CONFIG_ARM_NONSECURE_FIRMWARE	This option indicates that we are building a Zephyr image that is intended to execute in Non-Secure state. Execution of this image is triggered by Secure firmware that executes in Secure state. The option is only applicable to ARMv8-M MCUs that implement the Security Extension. This option enables Zephyr to include code that executes in Non-Secure state only, as well as to exclude code that is designed to execute only in Secure state. Code executing in Non-Secure state has no access to Secure resources of the Cortex-M MCU, and, therefore, it shall avoid accessing them.
CONFIG_ARM_NSC_REGION_BASE_ADDRESS	Start address of Non-Secure Callable section. Notes: - The default value (i.e. when the user does not configure the option explicitly) instructs the linker script to place the Non-Secure Callable section, automatically, inside the .text area. - Certain requirements/restrictions may apply regarding the size and the alignment of the starting address for a Non-Secure Callable section, depending on the available security attribution unit (SAU or IDAU) for a given SOC.
CONFIG_ARM_SECURE_BUSFAULT_HARDFAULT_NMI	Force NMI, HardFault, and BusFault (in Mainline ARMv8-M) exceptions as Secure exceptions.
CONFIG_ARM_SECURE_FIRMWARE	This option indicates that we are building a Zephyr image that is intended to execute in Secure state. The option is only applicable to ARMv8-M MCUs that implement the Security Extension. This option enables Zephyr to include code that executes in Secure state, as well as to exclude code that is designed to execute only in Non-secure state. Code executing in Secure state has access to both the Secure and Non-Secure resources of the Cortex-M MCU. Code executing in Non-Secure state may trigger Secure Faults, if Secure MCU resources are accessed from the Non-Secure state. Secure Faults may only be handled by code executing in Secure state.
CONFIG_ARM_STACK_PROTECTION	This option enables either: - The built-in Stack Pointer limit checking, or - the MPU-based stack guard to cause a system fatal error if the bounds of the current process stack are overflowed. The two stack guard options are mutually exclusive. The selection of the built-in Stack Pointer limit checking is prioritized over the MPU-based stack guard. The developer still has the option to manually select the MPU-based stack guard, if this is desired.
CONFIG_ARM_TRUSTZONE_M	Platform has support for ARM TrustZone-M.
CONFIG_ASSEMBLER_ISA_THUMB2	This helper symbol specifies the default target instruction set for the assembler. When only the Thumb-2 ISA is supported (i.e. on Cortex-M cores), the assembler must use the Thumb-2 instruction set. When both the Thumb-2 and ARM ISAs are supported (i.e. on Cortex-A and Cortex-R cores), the assembler must use the ARM instruction set because the architecture assembly code makes use of the ARM instructions.
CONFIG_BIG_ENDIAN	This option tells the build system that the target system is big-endian. Little-endian architecture is the default and should leave this option unselected. This option is selected by arch/$ARCH/Kconfig, soc//Kconfig, or boards//Kconfig and the user should generally avoid modifying it. The option is used to select linker script OUTPUT_FORMAT and command line option for gen_isr_tables.py.
CONFIG_BOARD	This option holds the name of the board and is used to locate the files related to the board in the source tree (under boards/). The Board is the first location where we search for a linker.ld file, if not found we look for the linker file in soc/<arch>/<family>/<series>
CONFIG_BUILTIN_STACK_GUARD	Enable Thread/Interrupt Stack Guards via built-in Stack Pointer limit checking. The functionality must be supported by HW.
CONFIG_CACHE_MANAGEMENT	This links in the cache management functions (for d-cache and i-cache where possible).
CONFIG_CLFLUSH_DETECT	This option should be enabled if it is not known in advance whether the CPU supports the CLFLUSH instruction or not. The CPU is queried at boot time to determine which of the multiple implementations of sys_cache_flush() linked into the image is the correct one to use. If the CPU’s support (or lack thereof) of CLFLUSH is known in advance, then disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED	An implementation of sys_cache_flush() that uses CLFLUSH is made available, instead of the one using WBINVD. This option should only be enabled if it is known in advance that the CPU supports the CLFLUSH instruction. It disables runtime detection of CLFLUSH support thereby reducing both memory footprint and boot time.
CONFIG_CMSIS_THREAD_MAX_STACK_SIZE	Mention max stack size threads can be allocated in CMSIS RTOS application.
CONFIG_CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE	Mention dynamic stack size threads are allocated in CMSIS RTOS V2 application.
CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE	Mention max stack size threads can be allocated in CMSIS RTOS V2 application.
CONFIG_CODE_DENSITY	Enable code density option to get better code density
CONFIG_COMPILER_ISA_THUMB2	This option configures the compiler to compile all C/C++ functions using the Thumb-2 instruction set. N.B. The scope of this symbol is not necessarily limited to the C and C++ languages; in fact, this symbol refers to all forms of “compiled” code. When an additional natively-compiled language support is added in the future, this symbol shall also specify the Thumb-2 instruction set for that language.
CONFIG_COMPRESSED_ISA
CONFIG_CORE_E31	This option signifies the use of a core of the E31 family.
CONFIG_CORTEX_M_DWT	Enable and use the Data Watchpoint and Trace (DWT) unit for timing functions.
CONFIG_CPU_APOLLO_LAKE	This option signifies the use of a CPU from the Apollo Lake family.
CONFIG_CPU_ARCEM	This option signifies the use of an ARC EM CPU
CONFIG_CPU_ARCHS	This option signifies the use of an ARC HS CPU
CONFIG_CPU_ARCV2	This option signifies the use of a CPU of the ARCv2 family.
CONFIG_CPU_ATOM	This option signifies the use of a CPU from the Atom family.
CONFIG_CPU_CORTEX	This option signifies the use of a CPU of the Cortex family.
CONFIG_CPU_CORTEX_A	This option signifies the use of a CPU of the Cortex-A family.
CONFIG_CPU_CORTEX_A53	This option signifies the use of a Cortex-A53 CPU
CONFIG_CPU_CORTEX_A72	This option signifies the use of a Cortex-A72 CPU
CONFIG_CPU_CORTEX_M	This option signifies the use of a CPU of the Cortex-M family.
CONFIG_CPU_CORTEX_M0	This option signifies the use of a Cortex-M0 CPU
CONFIG_CPU_CORTEX_M0PLUS	This option signifies the use of a Cortex-M0+ CPU
CONFIG_CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP	This option signifies the Cortex-M0 has some mechanisms that can map the vector table to SRAM
CONFIG_CPU_CORTEX_M1	This option signifies the use of a Cortex-M1 CPU
CONFIG_CPU_CORTEX_M23	This option signifies the use of a Cortex-M23 CPU
CONFIG_CPU_CORTEX_M3	This option signifies the use of a Cortex-M3 CPU
CONFIG_CPU_CORTEX_M33	This option signifies the use of a Cortex-M33 CPU
CONFIG_CPU_CORTEX_M4	This option signifies the use of a Cortex-M4 CPU
CONFIG_CPU_CORTEX_M7	This option signifies the use of a Cortex-M7 CPU
CONFIG_CPU_CORTEX_M_HAS_BASEPRI	This option signifies the CPU has the BASEPRI register. The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Always present in CPUs that implement the ARMv7-M or ARM8-M Mainline architectures.
CONFIG_CPU_CORTEX_M_HAS_CMSE	This option signifies the Cortex-M CPU has the CMSE intrinsics.
CONFIG_CPU_CORTEX_M_HAS_DWT	This option signifies that the CPU implements the Data Watchpoint and Trace (DWT) unit specified by the ARMv7-M and above. While ARMv6-M does define a “DWT” unit, this is significantly different from the DWT specified by the ARMv7-M and above in terms of both feature set and register mappings.
CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS	This option signifies the CPU may trigger system faults (other than HardFault) with configurable priority, and, therefore, it needs to reserve a priority level for them.
CONFIG_CPU_CORTEX_M_HAS_SPLIM	This option signifies the CPU has the MSPLIM, PSPLIM registers. The stack pointer limit registers, MSPLIM, PSPLIM, limit the extend to which the Main and Process Stack Pointers, respectively, can descend. MSPLIM, PSPLIM are always present in ARMv8-M MCUs that implement the ARMv8-M Main Extension (Mainline). In an ARMv8-M Mainline implementation with the Security Extension the MSPLIM, PSPLIM registers have additional Secure instances. In an ARMv8-M Baseline implementation with the Security Extension the MSPLIM, PSPLIM registers have only Secure instances.
CONFIG_CPU_CORTEX_M_HAS_SYSTICK	This option is enabled when the CPU implements the SysTick timer.
CONFIG_CPU_CORTEX_M_HAS_VTOR	This option signifies the CPU has the VTOR register. The VTOR indicates the offset of the vector table base address from memory address 0x00000000. Always present in CPUs implementing the ARMv7-M or ARMv8-M architectures. Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline architectures (except for Cortex-M0/M1, where it is never implemented).
CONFIG_CPU_CORTEX_R	This option signifies the use of a CPU of the Cortex-R family.
CONFIG_CPU_CORTEX_R4	This option signifies the use of a Cortex-R4 CPU
CONFIG_CPU_CORTEX_R5	This option signifies the use of a Cortex-R5 CPU
CONFIG_CPU_CORTEX_R7	This option signifies the use of a Cortex-R7 CPU
CONFIG_CPU_EM4	If y, the SoC uses an ARC EM4 CPU
CONFIG_CPU_EM4_DMIPS	If y, the SoC uses an ARC EM4 DMIPS CPU
CONFIG_CPU_EM4_FPUDA	If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision floating-point and double assist instructions
CONFIG_CPU_EM4_FPUS	If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision floating-point extension
CONFIG_CPU_EM6	If y, the SoC uses an ARC EM6 CPU
CONFIG_CPU_HAS_DCLS	This option is enabled when the processor hardware is configured in Dual-redundant Core Lock-step (DCLS) topology.
CONFIG_CPU_HAS_FPU	This option is enabled when the CPU has hardware floating point unit.
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION	When enabled, this indicates that the CPU has a double floating point precision unit.
CONFIG_CPU_HAS_MMU	This hidden option is selected when the CPU has a Memory Management Unit (MMU).
CONFIG_CPU_HAS_MPU	This option is enabled when the CPU has a Memory Protection Unit (MPU).
CONFIG_CPU_HAS_TEE	This option is enabled when the CPU has support for Trusted Execution Environment (e.g. when it has a security attribution unit).
CONFIG_CPU_MINUTEIA	This option signifies the use of a CPU from the Minute IA family.
CONFIG_CPU_NIOS2_GEN2	This option signifies the use of a Nios II Gen 2 CPU
CONFIG_CUSTOM_SECTION_ALIGN	MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory wasting in linker scripts defined memory sections. Use this symbol to guarantee user custom section align size to avoid more memory used for respect alignment. But that needs carefully configure MPU region and sub-regions(ARMv7-M) to cover this feature.
CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE	Custom align size of memory section in linker scripts. Usually it should consume less alignment memory. Although this alignment size is configured by users, it must also respect the power of two regulation if hardware requires.
CONFIG_DCACHE_LINE_SIZE	Size in bytes of a CPU d-cache line. If this is set to 0 the value is obtained from the ‘d-cache-line-size’ DT property instead if present. Detect automatically at runtime by selecting DCACHE_LINE_SIZE_DETECT.
CONFIG_DCACHE_LINE_SIZE_DETECT	This option enables querying some architecture-specific hardware for finding the d-cache line size at the expense of taking more memory and code and a slightly increased boot time. If the CPU’s d-cache line size is known in advance, disable this option and manually enter the value for DCACHE_LINE_SIZE or set it in the DT using the ‘d-cache-line-size’ property.
CONFIG_DEMAND_PAGING	Enable demand paging. Requires architecture support in how the kernel is linked and the implementation of an eviction algorithm and a backing store for evicted pages.
CONFIG_DEMAND_PAGING_ALLOW_IRQ	Allow interrupts to be serviced while pages are being evicted or retrieved from the backing store. This is much better for system latency, but any code running in interrupt context that page faults will cause a kernel panic. Such code must work with exclusively pinned code and data pages. The scheduler is still disabled during this operation. If this option is disabled, the page fault servicing logic runs with interrupts disabled for the entire operation. However, ISRs may also page fault.
CONFIG_DISABLE_SSBD	This option will disable Speculative Store Bypass in order to mitigate against certain kinds of side channel attacks. Quoting the “Speculative Execution Side Channels” document, version 2.0: When SSBD is set, loads will not execute speculatively until the addresses of all older stores are known. This ensure s that a load does not speculatively consume stale data values due to bypassing an older store on the same logical processor. If enabled, this applies to all threads in the system. Even if enabled, will have no effect on CPUs that do not require this feature.
CONFIG_DISABLE_TCM_ECC	This option disables ECC checks on Tightly Coupled Memory.
CONFIG_DYNAMIC_DIRECT_INTERRUPTS	Direct interrupts are designed for performance-critical interrupt handling and do not go through all of the common interrupt handling code. This option enables the installation of interrupt service routines for direct interrupts at runtime. Note: this requires enabling support for dynamic interrupts in the kernel.
CONFIG_DYNAMIC_INTERRUPTS	Enable installation of interrupts at runtime, which will move some interrupt-related data structures to RAM instead of ROM, and on some architectures increase code size.
CONFIG_DYNAMIC_OBJECTS	Enabling this option allows for kernel objects to be requested from the calling thread’s resource pool, at a slight cost in performance due to the supplemental run-time tables required to validate such objects. Objects allocated in this way can be freed with a supervisor-only API call, or when the number of references to that object drops to zero.
CONFIG_EAGER_FPU_SHARING	This hidden option unconditionally saves/restores the FPU/SIMD register state on every context switch. Mitigates CVE-2018-3665, but incurs a performance hit. For vulnerable systems that process sensitive information in the FPU register set, should be used any time CONFIG_FPU is enabled, regardless if the FPU is used by one thread or multiple.
CONFIG_ENABLE_EXTENDED_IBRS	This option will enable the Extended Indirect Branch Restricted Speculation ‘always on’ feature. This mitigates Indirect Branch Control vulnerabilities (aka Spectre V2).
CONFIG_EXCEPTION_DEBUG	Print human-readable information about exception vectors, cause codes, and parameters, at a cost of code/data size for the human-readable strings.
CONFIG_EXTRA_EXCEPTION_INFO	Have exceptions print additional useful debugging information in human-readable form, at the expense of code size. For example, the cause code for an exception will be supplemented by a string describing what that cause code means.
CONFIG_FAULT_DUMP	Different levels for display information when a fault occurs. 2: The default. Display specific and verbose information. Consumes the most memory (long strings). 1: Display general and short information. Consumes less memory (short strings). 0: Off.
CONFIG_FLASH_BASE_ADDRESS	This option specifies the base address of the flash on the board. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration.
CONFIG_FLASH_SIZE	This option specifies the size of the flash in kB. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration.
CONFIG_FLOAT_HARD	This option enables the hard-float calling convention.
CONFIG_FPU	This option enables the hardware Floating Point Unit (FPU), in order to support using the floating point registers and instructions. When this option is enabled, by default, threads may use the floating point registers only in an exclusive manner, and this usually means that only one thread may perform floating point operations. If it is necessary for multiple threads to perform concurrent floating point operations, the “FPU register sharing” option must be enabled to preserve the floating point registers across context switches. Note that this option cannot be selected for the platforms that do not include a hardware floating point unit; the floating point support for those platforms is dependent on the availability of the toolchain- provided software floating point library.
CONFIG_FPU_SHARING	This option enables preservation of the hardware floating point registers across context switches to allow multiple threads to perform concurrent floating point operations. Note that on Cortex-M processors with the floating point extension we enable by default the FPU register sharing mode, as some GCC compilers may activate a floating point context by generating FP instructions for any thread, and that context must be preserved when switching such threads in and out. The developers can still disable the FP sharing mode in their application projects, and switch to Unshared FP registers mode, if it is guaranteed that the image code does not generate FP instructions outside the single thread context that is allowed to do so.
CONFIG_FP_FPU_DA
CONFIG_FP_HARDABI	This option selects the Floating point ABI in which hardware floating point instructions are generated and uses FPU-specific calling conventions
CONFIG_FP_SOFTABI	This option selects the Floating point ABI in which hardware floating point instructions are generated but soft-float calling conventions.
CONFIG_GDT_DYNAMIC	This option stores the GDT in RAM instead of ROM, so that it may be modified at runtime at the expense of some memory.
CONFIG_GEN_IRQ_START_VECTOR	On some architectures, part of the vector table may be reserved for system exceptions and is declared separately from the tables created by gen_isr_tables.py. When creating these tables, this value will be subtracted from CONFIG_NUM_IRQS to properly size them. This is a hidden option which needs to be set per architecture and left alone.
CONFIG_GEN_IRQ_VECTOR_TABLE	This option controls whether a platform using gen_isr_tables needs an interrupt vector table created. Only disable this if the platform does not use a vector table at all, or requires the vector table to be in a format that is not an array of function pointers indexed by IRQ line. In the latter case, the vector table must be supplied by the application or architecture code.
CONFIG_GEN_ISR_TABLES	This option controls whether a platform uses the gen_isr_tables script to generate its interrupt tables. This mechanism will create an appropriate hardware vector table and/or software IRQ table.
CONFIG_GEN_PRIV_STACKS	Selected if the architecture requires that privilege elevation stacks be allocated in a separate memory area. This is typical of arches whose MPUs require regions to be power-of-two aligned/sized. FIXME: This should be removed and replaced with checks against CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT, but both ARM and ARC changes will be necessary for this.
CONFIG_GEN_SW_ISR_TABLE	This option controls whether a platform using gen_isr_tables needs a software ISR table table created. This is an array of struct _isr_table_entry containing the interrupt service routine and supplied parameter.
CONFIG_GP_ALL_DATA	Use GP relative access for all data in the program, not just small data. Use this if your board has 64K or less of RAM.
CONFIG_GP_GLOBAL	Use global pointer relative offsets for small globals declared anywhere in the executable. Note that if any small globals that are put in alternate sections they must be declared in headers with proper __attribute__((section)) or the linker will error out.
CONFIG_GP_LOCAL	Use global pointer relative offsets for small globals declared in the same C file as the code that uses it.
CONFIG_GP_NONE	Do not use global pointer relative offsets at all
CONFIG_HARVARD	The ARC CPU can be configured to have two busses; one for instruction fetching and another that serves as a data bus.
CONFIG_HAS_DIV_INSTRUCTION
CONFIG_HAS_MULX_INSTRUCTION
CONFIG_HAS_MUL_INSTRUCTION
CONFIG_HW_STACK_PROTECTION	Select this option to enable hardware-based platform features to catch stack overflows when the system is running in privileged mode. If CONFIG_USERSPACE is not enabled, the system is always running in privileged mode. Note that this does not necessarily prevent corruption and assertions about the overall system state when a fault is triggered cannot be made.
CONFIG_ICACHE_LINE_SIZE	Size in bytes of a CPU i-cache line. If this is set to 0 the value is obtained from the ‘i-cache-line-size’ DT property instead if present. Detect automatically at runtime by selecting ICACHE_LINE_SIZE_DETECT.
CONFIG_ICACHE_LINE_SIZE_DETECT	This option enables querying some architecture-specific hardware for finding the i-cache line size at the expense of taking more memory and code and a slightly increased boot time. If the CPU’s i-cache line size is known in advance, disable this option and manually enter the value for ICACHE_LINE_SIZE or set it in the DT using the ‘i-cache-line-size’ property.
CONFIG_IDLE_STACK_SIZE	Depending on the work that the idle task must do, most likely due to power management but possibly to other features like system event logging (e.g. logging when the system goes to sleep), the idle thread may need more stack space than the default value.
CONFIG_IDT_NUM_VECTORS	This option specifies the number of interrupt vector entries in the Interrupt Descriptor Table (IDT). By default all 256 vectors are supported in an IDT requiring 2048 bytes of memory.
CONFIG_INCLUDE_RESET_VECTOR	Include the reset vector stub, which enables instruction/data caches and then jumps to __start. This code is typically located at the very beginning of flash memory. You may need to omit this if using the nios2-download tool since it refuses to load data anywhere other than RAM.
CONFIG_INIT_ARCH_HW_AT_BOOT	This option instructs Zephyr to force the initialization of the internal architectural state (for example ARCH-level HW registers and system control blocks) during boot to the reset values as specified by the corresponding architecture manual. The option is useful when the Zephyr firmware image is chain-loaded, for example, by a debugger or a bootloader, and we need to guarantee that the internal states of the architecture core blocks are restored to the reset values (as specified by the architecture). Note: the functionality is architecture-specific. For the implementation details refer to each architecture where this feature is supported.
CONFIG_IPM_CONSOLE_STACK_SIZE	Each instance of the IPM console receiver driver creates a worker thread to print out incoming messages from the remote CPU. Specify the stack size for these threads here.
CONFIG_IRQ_OFFLOAD	Enable irq_offload() API which allows functions to be synchronously run in interrupt context. Only useful for test cases that need to validate the correctness of kernel objects in IRQ context.
CONFIG_IRQ_OFFLOAD_INTNUM	The index of the software interrupt to be used for IRQ offload. Please note that in order for IRQ offload to work correctly the selected interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL.
CONFIG_IRQ_OFFLOAD_VECTOR	IDT vector to use for IRQ offload
CONFIG_ISA_ARM	From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets A32 instructions, known as Arm instructions in pre-Armv8 architectures, are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions are supported by both A-profile and R-profile architectures. A32 was traditionally used in applications requiring the highest performance, or for handling hardware exceptions such as interrupts and processor start-up. Much of its functionality was subsumed into T32 with the introduction of Thumb-2 technology.
CONFIG_ISA_THUMB2	From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php Thumb-2 technology is the instruction set underlying the ARM Cortex architecture which provides enhanced levels of performance, energy efficiency, and code density for a wide range of embedded applications. Thumb-2 technology builds on the success of Thumb, the innovative high code density instruction set for ARM microprocessor cores, to increase the power of the ARM microprocessor core available to developers of low cost, high performance systems. The technology is backwards compatible with existing ARM and Thumb solutions, while significantly extending the features available to the Thumb instructions set. This allows more of the application to benefit from the best in class code density of Thumb. For performance optimized code Thumb-2 technology uses 31 percent less memory to reduce system cost, while providing up to 38 percent higher performance than existing high density code, which can be used to prolong battery-life or to enrich the product feature set. Thumb-2 technology is featured in the processor, and in all ARMv7 architecture-based processors.
CONFIG_ISR_DEPTH	The more nesting allowed, the more room is required for IRQ stacks.
CONFIG_ISR_STACK_SIZE	This option specifies the size of the stack used by interrupt service routines (ISRs), and during kernel initialization.
CONFIG_ISR_SUBSTACK_SIZE	Number of bytes from the ISR stack to reserve for each nested IRQ level. Must be a multiple of 16 to main stack alignment. Note that CONFIG_ISR_SUBSTACK_SIZE * CONFIG_ISR_DEPTH must be equal to CONFIG_ISR_STACK_SIZE.
CONFIG_KERNEL_VM_BASE	Define the base of the kernel’s address space. By default, this is the same as the DT_CHOSEN_Z_SRAM physical base SRAM address from DTS, in which case RAM will be identity-mapped. Some architectures may require RAM to be mapped in this way; they may have just one RAM region and doing this makes linking much simpler, as at least when the kernel boots all virtual RAM addresses are the same as their physical address (demand paging at runtime may later modify this for non-pinned page frames). Otherwise, if RAM isn’t identity-mapped: 1. It is the architecture’s responsibility to transition the instruction pointer to virtual addresses at early boot before entering the kernel at z_cstart(). 2. The underlying architecture may impose constraints on the bounds of the kernel’s address space, such as not overlapping physical RAM regions if RAM is not identity-mapped, or the virtual and physical base addresses being aligned to some common value (which allows double-linking of paging structures to make the instruction pointer transition simpler). Zephyr does not implement a split address space and if multiple page tables are in use, they all have the same virtual-to-physical mappings (with potentially different permissions).
CONFIG_KERNEL_VM_OFFSET	Offset that the kernel image begins within its address space, if this is not the same offset from the beginning of RAM. Some care may need to be taken in selecting this value. In certain build-time cases, or when a physical address cannot be looked up in page tables, the equation: virt = phys + ((KERNEL_VM_BASE + KERNEL_VM_OFFSET) - SRAM_BASE_ADDRESS) Will be used to convert between physical and virtual addresses for memory that is mapped at boot. This uncommon and is only necessary if the beginning of VM and physical memory have dissimilar alignment.
CONFIG_KERNEL_VM_SIZE	Size of the kernel’s address space. Constraining this helps control how much total memory can be used for page tables. The difference between KERNEL_VM_BASE and KERNEL_VM_SIZE indicates the size of the virtual region for runtime memory mappings. This is needed for mapping driver MMIO regions, as well as special RAM mapping use-cases such as VSDO pages, memory mapped thread stacks, and anonymous memory mappings. The kernel itself will be mapped in here as well at boot. Systems with very large amounts of memory (such as 512M or more) will want to use a 64-bit build of Zephyr, there are no plans to implement a notion of “high” memory in Zephyr to work around physical RAM size larger than the defined bounds of the virtual address space.
CONFIG_KOBJECT_TEXT_AREA	Size of kernel object text area. Used in linker script.
CONFIG_LAZY_FPU_SHARING	This hidden option allows multiple threads to use the floating point registers, using logic to lazily save/restore the floating point register state on context switch. On Intel Core processors, may be vulnerable to exploits which allows malware to read the contents of all floating point registers, see CVE-2018-3665.
CONFIG_MAIN_STACK_SIZE	When the initialization is complete, the thread executing it then executes the main() routine, so as to reuse the stack used by the initialization, which would be wasted RAM otherwise. After initialization is complete, the thread runs main().
CONFIG_MAX_IRQ_LINES	This option specifies the number of IRQ lines in the system. It determines the size of the _irq_to_interrupt_vector_table, which is used to track the association between vectors and IRQ numbers.
CONFIG_MAX_THREAD_BYTES	Every kernel object will have an associated bitfield to store thread permissions for that object. This controls the size of the bitfield (in bytes) and imposes a limit on how many threads can be created in the system.
CONFIG_MAX_XLAT_TABLES	This option specifies the maximum numbers of translation tables. Based on this, translation tables are allocated at compile time and used at runtime as needed. If the runtime need exceeds preallocated numbers of translation tables, it will result in assert. Number of translation tables required is decided based on how many discrete memory regions (both normal and device memory) are present on given platform and how much granularity is required while assigning attributes to these memory regions.
CONFIG_MMU	This option is enabled when the CPU’s memory management unit is active and the arch_mem_map() API is available.
CONFIG_MMU_PAGE_SIZE	Size of memory pages. Varies per MMU but 4K is common. For MMUs that support multiple page sizes, put the smallest one here.
CONFIG_MPU	This option, when enabled, indicates to the core kernel that an MPU is enabled.
CONFIG_MPU_ALLOW_FLASH_WRITE	Enable this to allow MPU RWX access to flash memory
CONFIG_MPU_GAP_FILLING	This Kconfig option instructs the MPU driver to enforce a full kernel SRAM partitioning, when it programs the dynamic MPU regions (user thread stack, PRIV stack guard and application memory domains) during context-switch. We allow this to be a configurable option, in order to be able to switch the option off and have an increased number of MPU regions available for application memory domain programming. Notes: An increased number of MPU regions should only be required, when building with USERSPACE support. As a result, when we build without USERSPACE support, gap filling should always be required. When the option is switched off, access to memory areas not covered by explicit MPU regions is restricted to privileged code on an ARCH-specific basis. Refer to ARCH-specific documentation for more information on how this option is used.
CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS	This option is enabled when the MPU requires the active (i.e. enabled) MPU regions to be non-overlapping with each other.
CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT	This option is enabled when the MPU requires a power of two alignment and size for MPU regions.
CONFIG_MPU_STACK_GUARD	Enable thread stack guards via MPU. ARC supports built-in stack protection. If your core supports that, it is preferred over MPU stack guard. For ARC_MPU_VER == 2, it requires 2048 extra bytes and a strong start address alignment, this will bring big waste of memory, so no support for it.
CONFIG_MPU_STACK_GUARD_MIN_SIZE_FLOAT	Minimum size (and alignment when applicable) of an ARM MPU region, which guards the stack of a thread that is using the Floating Point (FP) context. The width of the guard is set to 128, to accommodate the length of a Cortex-M exception stack frame when the floating point context is active. The FP context is only stacked in sharing FP registers mode, therefore, the option is applicable only when FPU_SHARING is selected.
CONFIG_MULTIBOOT	Embed a multiboot header in the output executable. This is used by some boot loaders (e.g., GRUB) when loading Zephyr. It is safe to leave this option on if you’re not sure. It only expands the text segment by 12-16 bytes and is typically ignored if not needed.
CONFIG_MULTIBOOT_FRAMEBUF	Multiboot framebuffer support
CONFIG_MULTIBOOT_FRAMEBUF_X	Multiboot framebuffer X pixels
CONFIG_MULTIBOOT_FRAMEBUF_Y	Multiboot framebuffer Y pixels
CONFIG_MULTIBOOT_INFO	Multiboot passes a pointer to an information structure to the kernel entry point. Some drivers (e.g., the multiboot framebuffer display driver) need to refer to information in this structure, and so set this option to preserve the data in a permanent location.
CONFIG_MULTIBOOT_MEMMAP	Use the multiboot memory map if the loader provides one.
CONFIG_NESTED_INTERRUPTS	This option enables support for nested interrupts.
CONFIG_NET_RX_STACK_SIZE	Set the RX thread stack size in bytes. The RX thread is waiting data from network. There is one RX thread in the system. This value is a baseline and the actual RX stack size might be bigger depending on what features are enabled.
CONFIG_NET_TX_STACK_SIZE	Set the TX thread stack size in bytes. The TX thread is waiting data from application. Each network interface will start one TX thread for sending network packets destined to it. This value is a baseline and the actual TX stack size might be bigger depending on what features are enabled.
CONFIG_NIOS2	Nios II Gen 2 architecture
CONFIG_NOCACHE_MEMORY	Add a “nocache” read-write memory section that is configured to not be cached. This memory section can be used to perform DMA transfers when cache coherence issues are not optimal or can not be solved using cache maintenance operations.
CONFIG_NO_UNUSED_STACK_INSPECTION	Selected if the architecture will generate a fault if unused stack memory is examined, which is the region between the current stack pointer and the deepest available address in the current stack region.
CONFIG_NUM_IRQS	Interrupts available will be 0 to NUM_IRQS-1. The minimum value is 17 as the first 16 entries in the vector table are for CPU exceptions. The BSP must provide a valid default. This drives the size of the vector table.
CONFIG_NUM_IRQ_PRIO_LEVELS	Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. The minimum value is 1. The BSP must provide a valid default for proper operation.
CONFIG_PCIE_MMIO_CFG	Selects the use of the memory-mapped PCI Express Extended Configuration Space instead of the traditional 0xCF8/0xCFC IO Port registers.
CONFIG_PIC_DISABLE	This option disables all interrupts on the legacy i8259 PICs at boot.
CONFIG_PLATFORM_SPECIFIC_INIT	The platform specific initialization code (z_platform_init) is executed at the beginning of the startup code (__start).
CONFIG_PMP_POWER_OF_TWO_ALIGNMENT	This option will reduce the PMP slot number usage but increase the memory consumption.
CONFIG_PMP_SLOT	Depend of the arch/board. Take care to don’t put value higher than the Hardware allow you.
CONFIG_PMP_STACK_GUARD	Enable Thread Stack Guards via PMP
CONFIG_PMP_STACK_GUARD_MIN_SIZE	Minimum size (and alignment when applicable) of an stack guard region, which guards the stack of a thread. The width of the guard is set to 4, to accommodate the riscv granularity.
CONFIG_PRIVILEGED_STACK_SIZE	This option sets the privileged stack region size that will be used in addition to the user mode thread stack. During normal execution, this region will be inaccessible from user mode. During system calls, this region will be utilized by the system call. This value must be a multiple of the minimum stack alignment.
CONFIG_REBOOT_RST_CNT	Reboot via the RST_CNT register, going back to BIOS.
CONFIG_RESET_VECTOR_IN_BOOTLOADER	Reset vector code can be either linked in the bootloader or the application binary. Select “y” to link it into the bootloader.
CONFIG_RGF_NUM_BANKS	The ARC CPU can be configured to have more than one register bank. If fast interrupts are supported (FIRQ), the 2nd register bank, in the set, will be used by FIRQ interrupts. If fast interrupts are supported but there is only 1 register bank, the fast interrupt handler must save and restore general purpose registers.
CONFIG_RISCV	RISCV architecture
CONFIG_RISCV_GENERIC_TOOLCHAIN	Compile using generic riscv32 toolchain. Allow SOCs that have custom extended riscv ISA to still compile with generic riscv32 toolchain.
CONFIG_RISCV_HAS_CPU_IDLE	Does SOC has CPU IDLE instruction
CONFIG_RISCV_PMP	MCU implements Physical Memory Protection. Memory protection against read-only area writing is natively supported on real HW.
CONFIG_RISCV_SOC_CONTEXT_SAVE	Enable low-level SOC-specific context management, for SOCs with extra state that must be saved when entering an interrupt/exception, and restored on exit. If unsure, leave this at the default value. Enabling this option requires that the SoC provide a soc_context.h header which defines the following macros: SOC_ESF_MEMBERS: structure component declarations to allocate space for. The last such declaration should not end in a semicolon, for portability. The generic RISC-V architecture code will allocate space for these members in a “struct soc_esf” type (typedefed to soc_esf_t), which will be available if arch.h is included. SOC_ESF_INIT: structure contents initializer for struct soc_esf state. The last initialized member should not end in a comma. The generic architecture IRQ wrapper will also call __soc_save_context and __soc_restore_context routines at ISR entry and exit, respectively. These should typically be implemented in assembly. If they were C functions, they would have these signatures: void __soc_save_context(soc_esf_t *state); void __soc_restore_context(soc_esf_t *state); The calls obey standard calling conventions; i.e., the state pointer address is in a0, and ra contains the return address.
CONFIG_RISCV_SOC_INTERRUPT_INIT	Enable SOC-based interrupt initialization (call soc_interrupt_init, within _IntLibInit when enabled)
CONFIG_RISCV_SOC_OFFSETS	Enabling this option requires that the SoC provide a soc_offsets.h header which defines the following macros: GEN_SOC_OFFSET_SYMS(): a macro which expands to GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls to ensure offset macros for SOC_ESF_MEMBERS are defined in offsets.h. The last one should not end in a semicolon. See gen_offset.h for more details.
CONFIG_RUNTIME_NMI	The kernel provides a simple NMI handler that simply hangs in a tight loop if triggered. This fills the requirement that there must be an NMI handler installed when the CPU boots. If a custom handler is needed, enable this option and attach it via _NmiHandlerSet().
CONFIG_SCHED_IPI_VECTOR	IDT vector to use for scheduler IPI
CONFIG_SET_GDT	This option sets up the GDT as part of the boot process. However, this may conflict with some security scenarios where the GDT is already appropriately set by an earlier bootloader stage, in which case this should be disabled. If disabled, the global _gdt pointer will not be available.
CONFIG_SIMULATOR_XTENSA	Specify if the board configuration should be treated as a simulator.
CONFIG_SJLI_TABLE_SIZE	The size of sjli (Secure Jump and Link Indexed) table. The code in normal mode call secure services in secure mode through sjli instruction.
CONFIG_SOC	SoC name which can be found under soc/<arch>/<soc name>. This option holds the directory name used by the build system to locate the correct linker and header files for the SoC.
CONFIG_SOC_FAMILY	SoC family name which can be found under soc/<arch>/<family>. This option holds the directory name used by the build system to locate the correct linker and header files.
CONFIG_SOC_SERIES	SoC series name which can be found under soc/<arch>/<family>/<series>. This option holds the directory name used by the build system to locate the correct linker and header files.
CONFIG_SPARC	SPARC architecture
CONFIG_SPARC_CASA	Use CASA atomic instructions. Defined by SPARC V9 and available in some LEON processors.
CONFIG_SPARC_NWIN	Number of implemented register windows.
CONFIG_SRAM_BASE_ADDRESS	The SRAM base address. The default value comes from from /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files.
CONFIG_SRAM_REGION_PERMISSIONS	This option indicates that memory protection hardware is present, enabled, and regions have been configured at boot for memory ranges within the kernel image. If this option is turned on, certain areas of the kernel image will have the following access policies applied for all threads, including supervisor threads: All program text will be have read-only, execute memory permission All read-only data will have read-only permission, and execution disabled if the hardware supports it. All other RAM addresses will have read-write permission, and execution disabled if the hardware supports it. Options such as USERSPACE or HW_STACK_PROTECTION may additionally impose additional policies on the memory map, which may be global or local to the current running thread. This option may consume additional memory to satisfy memory protection hardware alignment constraints. If this option is disabled, the entire kernel will have default memory access permissions set, typically read/write/execute. It may be desirable to turn this off on MMU systems which are using the MMU for demand paging, do not need memory protection, and would rather not use up RAM for the alignment between regions.
CONFIG_SRAM_SIZE	The SRAM size in kB. The default value comes from /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files.
CONFIG_SSE	This option enables the use of SSE registers by threads.
CONFIG_SSE_FP_MATH	This option allows the compiler to generate SSEx instructions for performing floating point math. This can greatly improve performance when exactly the same operations are to be performed on multiple data objects; however, it can also significantly reduce performance when preemptive task switches occur because of the larger register set that must be saved and restored. Disabling this option means that the compiler utilizes only the x87 instruction set for floating point operations.
CONFIG_STACK_ALIGN_DOUBLE_WORD	This is needed to conform to AAPCS, the procedure call standard for the ARM. It wastes stack space. The option also enforces alignment of stack upon exception entry on Cortex-M3 and Cortex-M4 (ARMv7-M). Note that for ARMv6-M, ARMv8-M, and Cortex-M7 MCUs stack alignment on exception entry is enabled by default and it is not configurable.
CONFIG_STACK_GROWS_UP	Select this option if the architecture has upward growing thread stacks. This is not common.
CONFIG_SW_VECTOR_RELAY	When building a bootloader firmware this option adds a vector table relay handler and a vector relay table, to relay interrupts based on a vector table pointer. This is only required but not limited to Cortex-M Baseline CPUs with no hardware vector table relocation mechanisms (e.g. VTOR).
CONFIG_SW_VECTOR_RELAY_CLIENT	Another image has enabled SW_VECTOR_RELAY, and will be forwarding exceptions and HW interrupts to this image. Enable this option to make sure the vector table pointer in RAM is set properly by the image upon initialization.
CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE	System workqueue stack size
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC	This option specifies hardware clock.
CONFIG_SYS_HEAP_ALWAYS_BIG_MODE	The sys_heap allocator by default returns pointers to blocks which are guaranteed to be aligned to the pointer size. By enabling the “big chunks” mode, the returned blocks are guaranteed to be 8 byte aligned, also on 32-bit platforms. If this option is enabled, the “big chunks” mode will always be used by sys_heap.
CONFIG_TEST_EXTRA_STACKSIZE	Additional stack for tests on some platform where default is not enough.
CONFIG_TLB_IPI_VECTOR	IDT vector to use for TLB shootdown IPI
CONFIG_TRUSTED_EXECUTION_NONSECURE	Select this option to enable building a Non-Secure firmware image for a platform that supports Trusted Execution. A Non-Secure firmware image will execute in Non-Secure (Normal) state. Therefore, it shall not access CPU resources (memory areas, peripherals, interrupts etc.) belonging to the Secure domain.
CONFIG_TRUSTED_EXECUTION_SECURE	Select this option to enable building a Secure firmware image for a platform that supports Trusted Execution. A Secure firmware image will execute in Secure state. It may allow the CPU to execute in Non-Secure (Normal) state. Therefore, a Secure firmware image shall be able to configure security attributions of CPU resources (memory areas, peripherals, interrupts, etc.) as well as to handle faults, related to security violations. It may optionally allow certain functions to be called from the Non-Secure (Normal) domain.
CONFIG_USERSPACE	When enabled, threads may be created or dropped down to user mode, which has significantly restricted permissions and must interact with the kernel via system calls. See Zephyr documentation for more details about this feature. If a user thread overflows its stack, this will be caught and the kernel itself will be shielded from harm. Enabling this option may or may not catch stack overflows when the system is in privileged mode or handling a system call; to ensure these are always caught, enable CONFIG_HW_STACK_PROTECTION.
CONFIG_X86	x86 architecture
CONFIG_X86_64	Run in 64-bit mode
CONFIG_X86_BOUNDS_CHECK_BYPASS_MITIGATION	Hidden config to select arch-independent option to enable Spectre V1 mitigations by default if the CPU is not known to be immune to it.
CONFIG_X86_COMMON_PAGE_TABLE	If this option is enabled, userspace memory domains will not have their own page tables. Instead, context switching operations will modify page tables in place. This is much slower, but uses much less RAM for page tables.
CONFIG_X86_DYNAMIC_IRQ_STUBS	Installing interrupt handlers with irq_connect_dynamic() requires some stub code to be generated at build time, one stub per dynamic interrupt.
CONFIG_X86_ENABLE_TSS	This hidden option enables defining a Task State Segment (TSS) for kernel execution. This is needed to handle double-faults or do privilege elevation. It also defines a special TSS and handler for correctly handling double-fault exceptions, instead of just letting the system triple-fault and reset.
CONFIG_X86_EXCEPTION_STACK_SIZE	The exception stack(s) (one per CPU) are used both for exception processing and early kernel/CPU initialization. They need only support limited call-tree depth and must fit into the low core, so they are typically smaller than the ISR stacks.
CONFIG_X86_EXCEPTION_STACK_TRACE	Internal config to enable runtime stack traces on fatal exceptions.
CONFIG_X86_FP_USE_SOFT_FLOAT	Enable using software floating point operations.
CONFIG_X86_KERNEL_OFFSET	A lot of x86 that resemble PCs have many reserved physical memory regions within the first megabyte. Specify an offset from the beginning of RAM to load the kernel in physical memory, avoiding these regions. Note that this does not include the “locore” which contains real mode bootstrap code within the first 64K of physical memory. This value normally need to be page-aligned.
CONFIG_X86_KPTI	Implements kernel page table isolation to mitigate Meltdown exploits to read Kernel RAM. Incurs a significant performance cost for user thread interrupts and system calls, and significant footprint increase for additional page tables and trampoline stacks.
CONFIG_X86_MAX_ADDITIONAL_MEM_DOMAINS	The initial page tables at boot are pre-allocated, and used for the default memory domain. Instantiation of additional memory domains if common page tables are in use requires a pool of free pinned memory pages for constructing page tables. Zephyr test cases assume 3 additional domains can be instantiated.
CONFIG_X86_MEMMAP_ENTRIES	Maximum number of memory regions to hold in the memory map.
CONFIG_X86_MMU	This options enables the memory management unit present in x86 and creates a set of page tables at boot time that is runtime- mutable.
CONFIG_X86_NO_LAZY_FP	This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Lazy FP CPU vulnerability, as described in CVE-2018-3665.
CONFIG_X86_NO_MELTDOWN	This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Meltdown CPU vulnerability, as described in CVE-2017-5754.
CONFIG_X86_NO_SPECTRE_V1	This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Spectre V1, V1.1, V1.2, and swapgs CPU vulnerabilities as described in CVE-2017-5753, CVE-2018-3693, and CVE-2019-1125.
CONFIG_X86_NO_SPECTRE_V2	This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Spectre V2 CPU vulnerability, as described in CVE-2017-5715.
CONFIG_X86_NO_SPECTRE_V4	This hidden option should be set on a per-SOC basis to indicate that a particular SOC is not vulnerable to the Spectre V4 CPU vulnerability, as described in CVE-2018-3639.
CONFIG_X86_NO_SPECULATIVE_VULNERABILITIES	This hidden option should be set on a per-SOC basis to indicate that a particular SOC does not perform any kind of speculative execution, or is a newer chip which is immune to the class of vulnerabilities which exploit speculative execution side channel attacks.
CONFIG_X86_PAE	If enabled, use PAE-style page tables instead of 32-bit page tables. The advantage is support for the Execute Disable bit, at a cost of more memory for paging structures.
CONFIG_X86_STACK_PROTECTION	This option leverages the MMU to cause a system fatal error if the bounds of the current process stack are overflowed. This is done by preceding all stack areas with a 4K guard page.
CONFIG_X86_USERSPACE	This option enables APIs to drop a thread’s privileges down to ring 3, supporting user-level threads that are protected from each other and from crashing the kernel.
CONFIG_X86_USE_THREAD_LOCAL_STORAGE	Internal config to enable thread local storage.
CONFIG_X86_VERY_EARLY_CONSOLE	Non-emulated X86 devices often require special hardware to attach a debugger, which may not be easily available. This option adds a very minimal serial driver which gets initialized at the very beginning of z_cstart(), via arch_kernel_init(). This driver enables printk to emit messages to the 16550 UART port 0 instance in device tree. This mini-driver assumes I/O to the UART is done via ports.
CONFIG_XTENSA	Xtensa architecture
CONFIG_XTENSA_ENABLE_BACKTRACE	Enable this config option to print backtrace on panic exception
CONFIG_XTENSA_KERNEL_CPU_PTR_SR	Specify which special register to store the pointer to _kernel.cpus[] for the current CPU.
CONFIG_XTENSA_NO_IPC	Uncheck this if you core does not implement “SCOMPARE1” register and “s32c1i” instruction.
CONFIG_XTENSA_RESET_VECTOR	This option controls whether the initial reset vector code is built. This is always needed for the simulator. Real boards may already implement this in boot ROM.
CONFIG_XTENSA_USE_CORE_CRT1	SoC or boards might define their own __start by setting this setting to false.
CONFIG_ZERO_LATENCY_IRQS	The kernel may reserve some of the highest interrupts priorities in the system for its own use. These interrupts will not be masked by interrupt locking. When connecting interrupts the kernel will offset all interrupts to lower priority than those reserved by the kernel. Zero-latency interrupt can be used to set up an interrupt at the highest interrupt priority which will not be blocked by interrupt locking. Since Zero-latency ISRs will run in the same priority or possibly at higher priority than the rest of the kernel they cannot use any kernel functionality.