Zephyr SoC Configuration Options¶
Kconfig files describe build-time configuration options (called symbols
in Kconfig-speak), how they’re grouped into menus and sub-menus, and
dependencies between them that determine what configurations are valid.
Kconfig files appear throughout the directory tree. For example,
subsys/power/Kconfig defines power-related options.
This documentation is generated automatically from the Kconfig files by
the gen_kconfig_rest.py script. Click on symbols for more
information.
Configuration Options¶
Symbol name |
Help/prompt |
|---|---|
Second level interrupts are used to increase the number of addressable interrupts in a system. |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
|
This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 2nd level interrupt ISRs begins. This is typically allocated after ISRs for level 1 interrupts. |
|
Enable the MCUX ADC12 driver. |
|
Enable the MCUX ADC16 driver. |
|
Enable the MCUX LPADC driver. |
|
Enable support for NPCX ADC driver. In NPCX7 series, it includes a 10-bit resolution Analog-to-Digital Converter (ADC). Up to 10 voltage inputs can be measured and a internal voltage reference (VREF), 2.816V (typical) is used for measurement. |
|
Enable Atmel SAM0 MCU Family Analog-to-Digital Converter (ADC) driver. |
|
Enable Atmel SAM MCU Family Analog-to-Digital Converter (ADC) driver based on AFEC module. |
|
Enable the driver implementation for the stm32xx ADC |
|
Enable ADC driver for Microchip XEC MCU series. |
|
AHB clock divider |
|
Use the x86 local APIC as the system time source. |
|
This option specifies the IRQ used by the local APIC timer. |
|
If your CPU supports invariant TSC, and you know the ratio of the TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC timer frequency), then enable this for a much faster and more accurate z_timer_cycle_get_32(). |
|
TSC to local APIC timer frequency divisor (M) |
|
TSC to local APIC timer frequency multiplier (N) |
|
It’s possible that an architecture port cannot or does not want to use the provided k_busy_wait(), but instead must do something custom. It must enable this option in that case. |
|
This option specifies the IRQ priority used by the ARC timer. Lower values have higher priority. |
|
ARC is configured with ARC CONNECT which is a hardware for connecting multi cores. |
|
Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts with highest priority, status32 and pc will be saved in aux regs, other regs will be saved according to the number of register bank; If FIRQ is disabled, the handle of interrupts with highest priority will be same with other interrupts. |
|
ARC MPU has several versions. For MPU v2, the minimum region is 2048 bytes; For MPU v3, the minimum region is 32 bytes |
|
ARM clock divider |
|
This option specifies the amount of SRAM (measure in kB) reserved for a bootloader image, when either: - the Zephyr image itself is to act as the bootloader, or - Zephyr is a !XIP image, which implicitly assumes existence of a bootloader that loads the Zephyr !XIP image onto SRAM. |
|
FlexSPI serial NAND |
|
FlexSPI serial NOR |
|
SEMC parallel NAND |
|
SEMC parallel NOR |
|
This option specifies the name of UART device to be used for the Bluetooth monitor logging. |
|
Build an Intel HEX binary zephyr/zephyr.hex in the build directory. The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. |
|
This links in the cache management functions (for d-cache and i-cache where possible). |
|
Enable support for mcux flexcan driver. |
|
The DSP wall clock timer is a timer driven directly by external oscillator and is external to the CPU core(s). It is not as fast as the internal core clock, but provides a common and synchronized counter for all CPU cores (which is useful for SMP). |
|
Enable the ROM bootloader backdoor which starts the bootloader if the associated pin is at the correct logic level on reset. |
|
Set the active level of the pin selected for the bootloader backdoor. |
|
Set the pin that is level checked if the bootloader backdoor is enabled. |
|
Enable the serial bootloader which resides in ROM on CC13xx / CC26xx devices. |
|
This module implements a kernel device driver for the TI SimpleLink CC13X2_CC26X2 series Real Time Counter and provides the standard “system clock driver” interfaces. |
|
Prepend debug header, disabling flash verification |
|
Prepend debug header, disabling flash verification |
|
This option should be enabled if it is not known in advance whether the CPU supports the CLFLUSH instruction or not. The CPU is queried at boot time to determine which of the multiple implementations of sys_cache_flush() linked into the image is the correct one to use. If the CPU’s support (or lack thereof) of CLFLUSH is known in advance, then disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate. |
|
Enable support for hardware clock controller. Such hardware can provide clock for other subsystem, and thus can be also used for power efficiency by controlling their clock. Note that this has nothing to do with RTC. |
|
Enable driver for reset and clock control used in LPC11U6X MCUs |
|
Enable support for mcux ccm driver. |
|
Enable support for mcux mcg driver. |
|
Enable support for MCUX PCC driver. |
|
Enable support for mcux scg driver. |
|
Enable support for mcux sim driver. |
|
Enable support for mcux clock driver. |
|
Enable support for NPCX clock controller driver. |
|
Enable driver for Reset & Clock Control subsystem found in STM32 family of MCUs |
|
Set this option to use the internal high frequency RC oscillator as high frequency clock. |
|
Set this option to use the external high frequency crystal oscillator as high frequency clock. |
|
Set this option to use the external low frequency crystal oscillator as high frequency clock. |
|
Set the internal high frequency RC oscillator frequency in Hz. This should be set by the board’s defconfig. Only supported values may be used here. Setting this to 0, skips the configuration of the high frequency RC oscillator completely. This may be desired, if the bootloader already configured it properly or the device’s default clock source should be used with it’s default configuration. |
|
Set the external high frequency oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
Set the external low frequency oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
Enable code density option to get better code density |
|
Link code into external FlexSPI-controlled memory |
|
Link code into internal FlexSPI-controlled memory |
|
Link code into internal instruction tightly coupled memory (ITCM) |
|
Link code into external SEMC-controlled memory |
|
This module implements a kernel device driver for the Cortex-M processor SYSTICK timer and provides the standard “system clock driver” interfaces. |
|
Enable the IMX EPIT driver. |
|
Enable support for mcux General Purpose Timer (GPT) driver. |
|
Enable support for the MCUX Low Power Timer (LPTMR). |
|
Enable support for the MCUX Periodic Interrupt Timer (PIT). |
|
Enable support for mcux rtc driver. |
|
Build RTC driver for STM32 SoCs. Tested on STM32 F0, F2, F3, F4, L1, L4, F7, G0, G4, H7 series |
|
Enable the SAM0 series timer counter (TC) driver in 32-bit wide mode. |
|
Enable counter driver for Microchip XEC MCU series. Such driver will expose the basic timer devices present on the MCU. |
|
If y, the SoC uses an ARC EM4 CPU |
|
If y, the SoC uses an ARC EM4 DMIPS CPU |
|
If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision floating-point and double assist instructions |
|
If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision floating-point extension |
|
If y, the SoC uses an ARC EM6 CPU |
|
This option is enabled when the CPU has a Memory Protection Unit (MPU) in ARM flavor. |
|
MCU implements the ARM Security Attribution Unit (SAU). |
|
If enabled, this option signifies that the SoC will define and configure its own fixed MPU regions in the SoC definition. These fixed MPU regions are currently used to set Flash and SRAM default access policies and they are programmed at boot time. |
|
MCU implements the nRF (vendor-specific) Security Attribution Unit. (IDAU: “Implementation-Defined Attribution Unit”, in accordance with ARM terminology). |
|
This option is enabled when the CPU has a Memory Protection Unit (MPU) in NXP flavor. |
|
Enable STM32 HAL-based Cryptographic Accelerator driver. |
|
Enable the driver for the NXP Kinetis MCUX DAC. |
|
Enable the driver for the NXP Kinetis MCUX DAC32. |
|
Enables the Atmel SAM0 MCU Family Digital-to-Analog (DAC) driver. |
|
Device configuration data (DCD) provides a sequence of commands to the boot ROM to initialize components such as an SDRAM. |
|
File system on a SDHC card accessed over NXP USDHC. |
|
Enable support for mcux eLCDIF driver. |
|
DMA driver for MCUX series SoCs. |
|
DMA driver for MCUX LPC MCUs. |
|
DMA driver for Atmel SAM0 series MCUs. |
|
Enable Atmel SAM MCU Family Direct Memory Access (XDMAC) driver. |
|
DMA driver for STM32 series SoCs. |
|
Enable installation of interrupts at runtime, which will move some interrupt-related data structures to RAM instead of ROM, and on some architectures increase code size. |
|
This option enables the driver for the True Random Number Generator (TRNG) for TI SimpleLink CC13xx / CC26xx SoCs. |
|
This option enables the true random number generator (TRNG) driver based on the MCUX RNG driver on LPC Family. |
|
This option enables the random number generator accelerator (RNGA) driver based on the MCUX RNGA driver. |
|
This option enables the true random number generator (TRNG) driver based on the MCUX TRNG driver. |
|
This option enables the true random number generator (TRNG) driver based on the RV32M1 TRNG driver. |
|
Enable True Random Number Generator (TRNG) driver for Atmel SAM MCUs. |
|
This option enables the RNG processor, which is a entropy number generator, based on a continuous analog noise, that provides a entropy 32-bit value to the host when read. It is available for F4 (except STM32F401 & STM32F411), L4, F7, H7 and G4 series. |
|
Enable support for NPCX ESPI driver. The Intel Enhanced Serial Peripheral Interface (eSPI) provides a path for migrating host sub-devices via LPC to a lower pin count, higher bandwidth bus. So far, this driver supports all of functionalities beside flash channel support. It will be supported in the future. Please refer https://www.intel.com/content/www/us/en/support/articles/000020952/ software/chipset-software.html for more detail. |
|
Enable the Microchip XEC ESPI driver. |
|
Enable MCUX Ethernet driver. Note, this driver performs one shot PHY setup. There is no support for PHY disconnect, reconnect or configuration change. |
|
Enable Atmel SAM MCU Family Ethernet driver. |
|
This option specifies the base address of the flash on the board. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration. |
|
The flash config offset provides the boot ROM with the on-board flash type and parameters. The boot ROM requires a fixed flash conifg offset for FlexSPI device. |
|
This option specifies the size of the flash in kB. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration. |
|
FlexSPI configuration block consists of parameters regarding specific flash devices including read command sequence, quad mode enablement sequence (optional), etc. The boot ROM expectes FlexSPI configuration parameter to be presented in serail nor flash. |
|
This option enables the hardware Floating Point Unit (FPU), in order to support using the floating point registers and instructions. When this option is enabled, by default, threads may use the floating point registers only in an exclusive manner, and this usually means that only one thread may perform floating point operations. If it is necessary for multiple threads to perform concurrent floating point operations, the “FPU register sharing” option must be enabled to preserve the floating point registers across context switches. Note that this option cannot be selected for the platforms that do not include a hardware floating point unit; the floating point support for those platforms is dependent on the availability of the toolchain- provided software floating point library. |
|
On some architectures, part of the vector table may be reserved for system exceptions and is declared separately from the tables created by gen_isr_tables.py. When creating these tables, this value will be subtracted from CONFIG_NUM_IRQS to properly size them. This is a hidden option which needs to be set per architecture and left alone. |
|
This option controls whether a platform uses the gen_isr_tables script to generate its interrupt tables. This mechanism will create an appropriate hardware vector table and/or software IRQ table. |
|
This option controls whether a platform using gen_isr_tables needs a software ISR table table created. This is an array of struct _isr_table_entry containing the interrupt service routine and supplied parameter. |
|
Include GPIO drivers in system config |
|
GPIO as pin reset (reset button) |
|
Enable the TI SimpleLink CC13xx / CC26xx GPIO driver. |
|
Enable the GPIO driver on TI SimpleLink CC32xx boards |
|
Enable the Gecko gpio driver. |
|
Enable the IMX GPIO driver. |
|
Enable driver for Intel Apollo Lake SoC GPIO |
|
Enable the MCUX pinmux driver. |
|
Enable the MCUX IGPIO driver. |
|
Enable the MCUX LPC pinmux driver. |
|
Enable support for NPCX GPIO driver. |
|
Enable the RV32M1 GPIO driver. |
|
Enable support for the Atmel SAM ‘PORT’ GPIO controllers. |
|
Enable support for the Atmel SAM0 ‘PORT’ GPIO controllers. |
|
Enable support for the Atmel SAM4L ‘PORT’ GPIO controllers. |
|
Enable GPIO driver for STM32 line of MCUs |
|
Enable the Microchip XEC gpio driver. |
|
The ARC CPU can be configured to have two busses; one for instruction fetching and another that serves as a data bus. |
|
Has the divider for ARM |
|
Set if the multipurpose clock generator (MCG) module is present in the SoC. |
|
Set if the oscillator (OSC) module is present in the SoC. |
|
When enabled, indicates that SoC has an SWO output |
|
Selected when CCFG (Customer Configuration) registers appear at the end of flash |
|
This option specifies the size of the heap memory pool used when dynamically allocating memory using k_malloc(). The maximum size of the memory pool is only limited to available memory. A size of zero means that no heap memory pool is defined. |
|
This option selects High Precision Event Timer (HPET) as a system timer. |
|
Enable Atmel SAM0 hwinfo driver. |
|
Enable support for I2C on the TI SimpleLink CC13xx / CC26xx series. |
|
Enable the Design Ware I2C driver |
|
The maximum number of supported driver instances in device tree. |
|
Enable the SiLabs Gecko I2C bus driver. |
|
Enable the i.MX I2C driver. |
|
Enable I2C support on the LPC11U6X SoCs |
|
Enable the mcux I2C driver. |
|
Enable the mcux flexcomm i2c driver. |
|
Enable the mcux LPI2C driver. |
|
Enable support for NPCX I2C driver. The NPCX SMB/I2C modules provides full support for a two-wire SMBus/I2C synchronous serial interface. Each interface is a two-wire serial interface that is compatible with both Intel SMBus and Philips I2C physical layer. There are 8 SMBus modules and 10 buses in NPCX7 series. |
|
Enable the RV32M1 LPI2C driver. |
|
Enable the SAM0 series SERCOM I2C driver. |
|
Enable Atmel SAM MCU Family (TWI) I2C bus driver. |
|
Enable Atmel SAM MCU Family (TWIHS) I2C bus driver. |
|
Enable Atmel SAM MCU Family (TWIM) I2C bus driver. |
|
Enable the Microchip XEC I2C driver. |
|
Enable Inter Sound (I2S) bus driver for Atmel SAM MCU family based on Synchronous Serial Controller (SSC) module. |
|
Enable I2S support on the STM32 family of processors. (Tested on the STM32F4 series) |
|
ESP32 as target board |
|
Depending on the work that the idle task must do, most likely due to power management but possibly to other features like system event logging (e.g. logging when the system goes to sleep), the idle thread may need more stack space than the default value. |
|
TI CC13xx / CC26xx IEEE 802.15.4 driver support |
|
TI CC13xx / CC26xx IEEE 802.15.4g driver support |
|
NXP KW41Z Driver support |
|
nRF52 series IEEE 802.15.4 Driver |
|
The Image Vector Table (IVT) provides the boot ROM with pointers to the application entry point and device configuration data. The boot ROM requires a fixed IVT offset for each type of boot device. |
|
Initialize ARM PLL |
|
Initialize Audio PLL |
|
If y, the Ethernet PLL is initialized. Always enabled on e.g. MIMXRT1021 - see commit 17f4d6bec7 (“soc: nxp_imx: fix ENET_PLL selection for MIMXRT1021”). |
|
Initialize SYS PLL |
|
Initialize USB1 PLL |
|
Initialize Video PLL |
|
IPG clock divider |
|
Include interrupt-based inter-processor mailboxes drivers in system configuration |
|
Driver for the Intra-DSP Communication (IDC) channel for cross SoC communications. |
|
Enable console over Inter-processor Mailbox. |
|
Driver for NXP i.MX messaging unit |
|
Driver for stm32 IPCC mailboxes |
|
The index of the software interrupt to be used for IRQ offload. Please note that in order for IRQ offload to work correctly the selected interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL. |
|
Configures the maximum number of clients allowed per shared instance of the shared interrupt driver. To conserve RAM set this value to the lowest practical value. this software interrupt default set on by device tree. |
|
This option specifies the divide value for the K22 bus clock from the system clock. |
|
This option specifies the divide value for the K22 processor core clock from the system clock. |
|
This option specifies the divide value for the K64 flash clock from the system clock. |
|
This option specifies the divide value for the K22 FlexBus clock from the system clock. |
|
This option specifies the divide value for the K6X bus clock from the system clock. |
|
This option specifies the divide value for the K6X processor core clock from the system clock. |
|
This option specifies the divide value for the K6X flash clock from the system clock. |
|
This option specifies the divide value for the K6X FlexBus clock from the system clock. |
|
This options enables support for High Speed RUN mode on K66F SoC. |
|
This option specifies the divide value for the K8x bus clock from the system clock. |
|
This option specifies the divide value for the K8x processor core clock from the system clock. |
|
This option specifies the divide value for the K8x flash clock from the system clock. |
|
This option specifies the divide value for the K8x FlexBus clock from the system clock. |
|
Code entry symbol, to be set at linking phase. |
|
Include the 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the FTFx module. |
|
Configures the reset value of the FDPROT register for FlexNVM devices. For program flash only devices, this byte is reserved. |
|
Configures the reset value of the FEPROT register for FlexNVM devices. For program flash only devices, this byte is reserved. |
|
Configures the reset value of the FOPT register, which includes boot, NMI, and EzPort options. |
|
Configures the reset value of the FSEC register, which includes backdoor key access, mass erase, factory access, and flash security options. |
|
Kinetis flash configuration field offset |
|
Enable the code cache |
|
Enable the Microchip XEC Kscan IO driver. |
|
This option specifies the divide value for the KV5X bus clock from the system clock. |
|
This option specifies the divide value for the KV5X processor core clock from the system clock. |
|
This option specifies the divide value for the KV5X flash clock from the system clock. |
|
This option specifies the divide value for the KV5X FlexBus clock from the system clock. |
|
This option specifies the divide value for the KW2xD bus clock from the system clock. |
|
This option specifies the divide value for the KW2xD processor core clock from the system clock. |
|
This option specifies the divide value for the KW2xD flash clock from the system clock. |
|
Enable the Gecko leuart driver. |
|
Global switch for the logger, when turned off log calls will not be compiled in. |
|
Enable backend for the host trace protocol of the Intel ADSP family of audio processors |
|
Enable backend in xtensa simulator |
|
LOG_PRINTK messages are formatted in place and logged unconditionally. |
|
When the initialization is complete, the thread executing it then executes the main() routine, so as to reuse the stack used by the initialization, which would be wasted RAM otherwise. After initialization is complete, the thread runs main(). |
|
The maximum number of interrupt inputs to any aggregator in the system. |
|
Selects the amount to divide down the fast internal reference clock. The resulting frequency must be in the range 31.25 kHz to 4 MHz. |
|
Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. |
|
Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must be in the range of 2 MHz to 4 MHz. |
|
Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits establish the multiplication factor (M) applied to the reference clock frequency. |
|
This module implements a kernel device driver for the Microchip XEC series RTOS timer and provides the standard “system clock driver” interfaces. |
|
Enable STM32 Flexible Memory Controller. |
|
Number of multiprocessing-capable cores available to the multicpu API and SMP features. |
|
Multiple levels of interrupts are normally used to increase the number of addressable interrupts in a system. For example, if two levels are used, a second level interrupt aggregator would combine all interrupts routed to it into one IRQ line in the first level interrupt controller. If three levels are used, a third level aggregator combines its input interrupts into one IRQ line at the second level. The number of interrupt levels is usually determined by the hardware. (The term “aggregator” here means “interrupt controller”.) |
|
The device name to get bindings from in the sample application. |
|
Add support for Ethernet, enabling selecting relevant hardware drivers. If NET_SLIP_TAP is selected, NET_L2_ETHERNET will enable to fully simulate Ethernet through SLIP. |
|
Add support for low rate WPAN IEEE 802.15.4 technology. |
|
P0.9 and P0.10 are usually reserved for NFC. This option switch them to normal GPIO mode. HW enabling happens once in the device lifetime, during the first system startup. Disabling this option will not switch back these pins to NFCT mode. Doing this requires UICR erase prior to flashing device using the image which has this option disabled. |
|
Due to Anomaly 132 LF RC source may not start if restarted in certain window after stopping (230 us to 330 us). Software reset also stops the clock so if clock is initiated in certain window, the clock may also fail to start at reboot. A delay is added before starting LF clock to ensure that anomaly conditions are not met. Delay should be long enough to ensure that clock is started later than 330 us after reset. If crystal oscillator (XO) is used then low frequency clock initially starts with RC and then seamlessly switches to XO which has much longer startup time thus, depending on application, workaround may also need to be applied. Additional drivers initialization increases initialization time and delay may be shortened. Workaround is disabled by setting delay to 0. |
|
This anomaly applies to IC Rev. Engineering A, build codes QKAA-AB0. This config MUST be enabled if there is a chance the code will be run on nRF5340 Engineering A. Enabling this config is safe on other nRF5340 variants, but might increase flash size. The workaround involves adding run-time checks when using the SPU, and aligning regions on 32 KiB instead of 16 KiB if they are to be locked with the SPU. More info: https://infocenter.nordicsemi.com/topic/errata_nRF5340_EngA/ERR/nRF5340/EngineeringA/latest/anomaly_340_19.html?cp=3_0_1_0_1_15 |
|
FLASH region size for the NRF_ACL peripheral. |
|
FLASH region size for the NRF_BPROT peripheral (nRF52). |
|
Instruction and Data cache is available on nRF5340 CPUAPP (Application MCU). It may only be accessed by Secure code. Instruction cache only (I-Cache) is available in nRF5340 CPUNET (Network MCU). |
|
Enable the instruction cache (I-Cache) |
|
FLASH region size for the NRF_MPU peripheral. |
|
This module implements a kernel device driver for the nRF Real Time Counter NRF_RTC1 and provides the standard “system clock driver” interfaces. |
|
FLASH region size for the NRF_SPU peripheral |
|
RAM region size for the NRF_SPU peripheral |
|
The number of level 2 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 2 interrupts. |
|
Interrupts available will be 0 to NUM_IRQS-1. The minimum value is 17 as the first 16 entries in the vector table are for CPU exceptions. The BSP must provide a valid default. This drives the size of the vector table. |
|
Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. The minimum value is 1. The BSP must provide a valid default for proper operation. |
|
Enable data structures required by the boot ROM to boot the application from an external flash device. |
|
Enable data structures required by the boot ROM to boot the application from an external flash device. |
|
Set this option to use the oscillator in external reference clock mode. |
|
Set this option to use the oscillator in high-gain mode. |
|
Set this option to use the oscillator in low-power mode. |
|
Set the external oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
Selects the use of the memory-mapped PCI Express Extended Configuration Space instead of the traditional 0xCF8/0xCFC IO Port registers. |
|
Enable the Microchip XEC PECI IO driver. |
|
Enable the TI SimpleLink CC13xx / CC26xx pinmux driver. |
|
Pinmux driver initialization priority. Pinmux driver almost certainly should be initialized before the rest of hardware devices (which may need specific pins already configured for them), and usually after generic GPIO drivers. Thus, its priority should be between KERNEL_INIT_PRIORITY_DEFAULT and KERNEL_INIT_PRIORITY_DEVICE. There are exceptions to this rule for particular boards. Don’t change this value unless you know what you are doing. |
|
Enable the MCUX pinmux driver. |
|
Enable the MCUX LPC pinmux driver. |
|
Enable support for NPCX pinmux controller driver. |
|
Enable the RV32M1 pinmux driver. |
|
Enable support for the Atmel SAM0 PORT pin multiplexer. |
|
Enable pin multiplexer for STM32 MCUs |
|
Enable the Microchip XEC pinmux driver. |
|
This option enables the board to implement extra power management policies whenever the kernel becomes idle. The kernel informs the power management subsystem of the number of ticks until the next kernel timer is due to expire. |
|
This option enables the device power management interface. The interface consists of hook functions implemented by device drivers that get called by the power manager application when the system is going to suspend state or resuming from suspend state. This allows device drivers to do any necessary power management operations like turning off device clocks and peripherals. The device drivers may also save and restore states in these hook functions. |
|
Enable the Microchip XEC PS2 IO driver. The driver also depends on the KBC 8042 keyboard controller. |
|
Enable support for i.MX pwm driver. |
|
Enable mcux pwm driver. |
|
Enable support for mcux ftm pwm driver. |
|
Enable the MCUX Pulse Width Timer (PWT) PWM capture driver. |
|
Enable the MCUX TPM PWM driver. |
|
Enable support for NPCX PWM driver. |
|
Enable the RV32M1 TPM PWM driver. |
|
Enable PWM driver for Atmel SAM MCUs. |
|
Enable PWM driver for Atmel SAM0 MCUs using the TCC timer/counter. |
|
This option enables the PWM driver for STM32 family of processors. Say y if you wish to use PWM port on STM32 MCU. |
|
Enable driver to utilize PWM on the Microchip XEC IP block. |
|
The ARC CPU can be configured to have more than one register bank. If fast interrupts are supported (FIRQ), the 2nd register bank, in the set, will be used by FIRQ interrupts. If fast interrupts are supported but there is only 1 register bank, the fast interrupt handler must save and restore general purpose registers. |
|
Compile using generic riscv32 toolchain. Allow SOCs that have custom extended riscv ISA to still compile with generic riscv32 toolchain. |
|
Does SOC has CPU IDLE instruction |
|
Does the SOC provide support for a Platform Level Interrupt Controller |
|
Enable low-level SOC-specific context management, for SOCs with extra state that must be saved when entering an interrupt/exception, and restored on exit. If unsure, leave this at the default value. Enabling this option requires that the SoC provide a soc_context.h header which defines the following macros:
The generic architecture IRQ wrapper will also call __soc_save_context and __soc_restore_context routines at ISR entry and exit, respectively. These should typically be implemented in assembly. If they were C functions, they would have these signatures:
The calls obey standard calling conventions; i.e., the state pointer address is in a0, and ra contains the return address. |
|
Enable SOC-based interrupt initialization (call soc_interrupt_init, within _IntLibInit when enabled) |
|
Enabling this option requires that the SoC provide a soc_offsets.h header which defines the following macros:
|
|
By default BL2 header size in TF-M is 0x400. ROM_START_OFFSET needs to be updated if TF-M switches to use a different header size for BL2. |
|
MEC1501 RTOS timer |
|
Select this option to enable support for the RV32M1 INTMUX driver. This provides a level 2 interrupt controller for the SoC. The INTMUX peripheral combines level 2 interrupts into eight channels; each channel has its own level 1 interrupt to the core. |
|
Enable support for INTMUX channel 0. |
|
Enable support for INTMUX channel 1. |
|
Enable support for INTMUX channel 2. |
|
Enable support for INTMUX channel 3. |
|
Enable support for INTMUX channel 4. |
|
Enable support for INTMUX channel 5. |
|
Enable support for INTMUX channel 6. |
|
Enable support for INTMUX channel 7. |
|
True if the architecture supports a call to arch_sched_ipi() to broadcast an interrupt that will call z_sched_ipi() on other CPUs in the system. Required for k_thread_abort() to operate with reasonable latency (otherwise we might have to wait for the other thread to take an interrupt, which can be arbitrarily far in the future). |
|
This is the address the second core will boot from. Additionally this address is where we will copy the SECOND_IMAGE to. We default this to the base of SRAM1. |
|
Driver for second core startup |
|
This points to the image file for the the binary code that will be used by the second core. |
|
Enable options for serial drivers. |
|
When true, kernel will be built with SMP support, allowing more than one CPU to schedule Zephyr tasks at a time. |
|
SoC name which can be found under soc/<arch>/<soc name>. This option holds the directory name used by the build system to locate the correct linker and header files for the SoC. |
|
Intel Apollo Lake Soc |
|
Synopsys ARC EM Software Development Platform |
|
Synopsys ARC HSDK SoC |
|
Synopsys ARC IoT SoC |
|
ARM Cortex-M1 DesignStart FPGA |
|
ARM Cortex-M3 DesignStart FPGA |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Says y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Says y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This is the divider (DIVA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 6, and DIVA == 1, PLL is running at 7 times of main clock. |
|
This is the multiplier (MULA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 6, and DIVA == 1, PLL is running at 7 times of main clock. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Says y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Says y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This is the divider (DIVA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 9, and DIVA == 1, PLL is running at 10 times of main clock. |
|
This is the multiplier (MULA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 9, and DIVA == 1, PLL is running at 10 times of main clock. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Says y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Says y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This is the divider (DIVA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 9, and DIVA == 1, PLL is running at 10 times of main clock. |
|
This is the multiplier (MULA) used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. With default of MULA == 9, and DIVA == 1, PLL is running at 10 times of main clock. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
OSCULP32K |
|
Say y to enable the external 32 kHZ crystal oscillator at startup. This can then be selected as the main clock source for the SOC. |
|
XOSC32K |
|
OSC8M |
|
Say y to enable the external crystal oscillator at startup. |
|
Say y to enable the external 32 kHZ crystal oscillator at startup. This can then be selected as the main clock source for the SOC. |
|
XOSC32K |
|
XOSC |
|
At reset ERASE pin is configured in System IO mode. Asserting the ERASE pin at ‘1’ will completely erase Flash memory. Setting this option will switch the pin to general IO mode giving control of the pin to the GPIO module. |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Say y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Say y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This divisor defines a ratio between processor clock (HCLK) and master clock (MCK): MCK = HCLK / MDIV |
|
This is the divider DIVA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. Setting DIVA=0 would disable PLL at boot, this is currently not supported. With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency. |
|
This is the multiplier MULA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. Setting MULA=0 would disable PLL at boot, this is currently not supported. With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
At reset ERASE pin is configured in System IO mode. Asserting the ERASE pin at ‘1’ will completely erase Flash memory. Setting this option will switch the pin to general IO mode giving control of the pin to the GPIO module. |
|
The main clock is being used to drive the PLL, and thus driving the processor clock. Say y if you want to use external crystal oscillator to drive the main clock. Note that this adds about a second to boot time, as the crystal needs to stabilize after power-up. The crystal used here can be from 3 to 20 MHz. Says n here will use the internal fast RC oscillator running at 12 MHz. |
|
Say y if you want to use external 32 kHz crystal oscillator to drive the slow clock. Note that this adds a few seconds to boot time, as the crystal needs to stabilize after power-up. Says n if you do not need accurate and precise timers. The slow clock will be driven by the internal fast RC oscillator running at 32 kHz. |
|
This divisor defines a ratio between processor clock (HCLK) and master clock (MCK): MCK = HCLK / MDIV |
|
This is the divider DIVA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. Setting DIVA=0 would disable PLL at boot, this is currently not supported. With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency. |
|
This is the multiplier MULA used by the PLL. The processor clock is (MAINCK * (MULA + 1) / DIVA). Board config file can override this settings for a particular board. Setting MULA=0 would disable PLL at boot, this is currently not supported. With default of MULA == 24, and DIVA == 1, PLL is running at 25 times the main clock frequency. |
|
For JTAG debugging CPU clock (HCLK) should not stop. In order to achieve this, make CPU go to Wait mode instead of Sleep mode while using external crystal oscillator for main clock. |
|
Intel ATOM SoC |
|
Broadcom BCM58400 |
|
Broadcom BCM58402 A72 |
|
Broadcom BCM58402 M7 |
|
ARM BEETLE R0 |
|
CC1352R |
|
CC2652R |
|
CC3220SF |
|
CC3235SF |
|
Enable nRF52 series System on Chip DC/DC converter. |
|
Enable nRF53 series System on Chip Application MCU DC/DC converter. |
|
Enable nRF53 series System on Chip High Voltage DC/DC converter. |
|
Enable nRF53 series System on Chip Network MCU DC/DC converter. |
|
This hidden option is set in the SoC configuration and indicates the Zephyr release that the SoC configuration will be removed. When set, any build for that SoC will generate a clearly visible deprecation warning. |
|
Intel Elkhart Lake Soc |
|
Synopsys ARC EM11D of EMSDP |
|
Synopsys ARC EM4 of EMSDP |
|
Synopsys ARC EM5D of EMSDP |
|
Synopsys ARC EM6 of EMSDP |
|
Synopsys ARC EM7D of EMSDP |
|
Synopsys ARC EM7D+ESP of EMSDP |
|
Synopsys ARC EM9D of EMSDP |
|
Synopsys ARC EM Starter Kit SoC |
|
Synopsys ARC EM11D of EMSK |
|
Synopsys ARC EM7D of EMSK |
|
Synopsys ARC EM9D of EMSK |
|
Enable the low-frequency oscillator (LFXO) functionality on XL1 and XL2 pins. This option must be enabled if either application or network core is to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular GPIOs. |
|
QuickLogic EOS S3 SoC |
|
ESP32 |
|
SoC family name which can be found under soc/<arch>/<family>. This option holds the directory name used by the build system to locate the correct linker and header files. |
|
omit prompt to signify a “hidden” option |
|
Enable Silicon Labs Gecko series internal flash driver. |
|
Enables the LPC IAP flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enables the MCUX flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enables the RV32M1 flash shim driver. WARNING: This driver will disable the system interrupts for the duration of the flash erase/write operations. This will have an impact on the overall system performance - whether this is acceptable or not will depend on the use case. |
|
Enable the Atmel SAM series internal flash driver. |
|
Set if the clock management unit (CMU) is present in the SoC. |
|
Set if the Core interrupt handling (CORE) HAL module is used. |
|
Set if the Ultra Low Energy Timer/Counter (CRYOTIMER) HAL module is used. |
|
Set if the Energy Management Unit (EMU) HAL module is used. |
|
Enable the on chip DC/DC regulator |
|
Bypass |
|
DC/DC Off |
|
DC/DC On |
|
Initial / Unconfigured |
|
Set if the General Purpose Input/Output (GPIO) HAL module is used. |
|
Set if the SoC is affected by errata RTCC_E201: “When the RTCC is configured with a prescaler, the CCV1 top value enable feature enabled by setting CCV1TOP in RTCC_CTRL fails to wrap the counter when RTCC_CNT is equal to RTCC_CC1_CCV, as intended.” |
|
If enabled, indicates that configuration of HFRCO frequency for this SOC is supported via FREQRANGE field. This is supported for e.g. efr32fg1p, efr32mg12p series. If disabled, indicates that configuration of HFRCO frequency for corresponding SOC is not supported via this field. This is the case for e.g. efm32hg, efm32wg series. |
|
If enabled, indicates that SoC allows to configure individual pin locations. This is supported by e.g. efr32fg1p, efr32mg12p series. If disabled, indicates that pin locations are configured in groups. This is supported by e.g. efm32hg, efm32wg series. |
|
Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used. |
|
Set if the Low Energy Timer (LETIMER) HAL module is used. |
|
Set if the Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) HAL module is used. |
|
Set if the Memory System Controller (MSC) HAL module is used. |
|
Set if the Peripheral Reflex System (PRS) HAL module is used. |
|
Set if the Reset Management Unit (RMU) HAL module is used. |
|
Set if the Real Time Counter (RTC) HAL module is used. |
|
Set if the Real Time Counter and Calendar (RTCC) HAL module is used. |
|
Set if the Secure Element (SE) HAL module is used. |
|
Set if the Timer/Counter (TIMER) HAL module is used. |
|
Set if the SoC has a True Random Number Generator (TRNG) module. |
|
Set if the Universal Synchronous Asynchronous Receiver/Transmitter (USART) HAL module is used. |
|
Set if the Watchdog Timer (WDOG) HAL module is used. |
|
GR716A LEON3 fault-tolerant microcontroller |
|
Should be selected if SoC provides custom method for retrieving timestamps and cycle count. |
|
Generic IA32 SoC |
|
Apollo Lake |
|
CAVS v1.8 SoC |
|
CAVS v2.0 SoC |
|
CAVS v2.5 SoC |
|
intel_s1000 |
|
ITE IT8XXX2 system implementation |
|
A LEON3 SOC which you can configure |
|
SOC_LPC11U66 |
|
SOC_LPC11U67 |
|
SOC_LPC11U68 |
|
SOC_LPC54114_M0 |
|
SOC_LPC54114_M4 |
|
SOC_LPC55S16 M33 |
|
SOC_LPC55S28 M33 |
|
SOC_LPC55S69 M33 [CPU 0] |
|
SOC_LPC55S69 M33 [CPU 1] |
|
M487 |
|
SOC_MCIMX6X_M4 |
|
SOC_MCIMX7_M4 |
|
JTAG port in SWD mode and SWV as tracing method. UART2 can be used, but ADC00-03 cannot. |
|
JTAG port in SWD mode and SWV as tracing method. UART2 cannot be used. ADC00-03 can be used. |
|
JTAG port is enabled in SWD mode. Refer to tracing options to see if ADC00-03 can be used or not. |
|
Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST# pin is ignored. All other JTAG pins can be used as GPIOs or other non-JTAG alternate functions. |
|
JTAG port in SWD mode. UART2 and ADC00-03 can be used. |
|
Use an external 32768 Hz clock source for PLL reference clock. Say y if you want to use an external source for the PLL 32KHz reference clock. Say n to use the +/-2% internal silicon oscillator. |
|
Choose a crystal as the external 32KHz source. Say y if you wish to use a crystal as the external 32KHz clock source. Saying n will select the 32KHZ_IN pin as the external 32KHz clock source. |
|
Choose external 32KHz crystal connection. Say y if the crystal is connected parallel between the XTAL1 and XTAL pins. Say n if the crystal is connected single ended to the XTAL2 pin or a 32KHz square wave is on XTAL2. |
|
MEC1501_HSZ |
|
This divisor defines a ratio between processor clock (HCLK) and master clock (MCK): HCLK = MCK / PROC_CLK_DIV Allowed divider values: 1, 3, 4, 16, and 48. |
|
By default these pins are not GPIOs, but HW controlled. Set this if VCI pin block HW logic is not required in the board design. |
|
Set this is if VTR3 power sourcejumper in the board is changed. |
|
MEC1701_QSZ |
|
SOC_MIMX8MM6 |
|
SOC_MIMXRT1011 |
|
SOC_MIMXRT1015 |
|
SOC_MIMXRT1021 |
|
SOC_MIMXRT1024 |
|
SOC_MIMXRT1051 |
|
SOC_MIMXRT1052 |
|
SOC_MIMXRT1061 |
|
SOC_MIMXRT1062 |
|
SOC_MIMXRT1064 |
|
SOC_MIMXRT685S M33 |
|
SOC_MK22F51212 |
|
SOC_MK64F12 |
|
SOC_MK66F18 |
|
MK80F25615 |
|
MK82F25615 |
|
MKE14F16 |
|
MKE16F16 |
|
MKE18F16 |
|
SOC_MKL25Z4 |
|
MKV56F24 |
|
MKV58F24 |
|
SOC_MKW22D5 |
|
SOC_MKW24D5 |
|
SOC_MKW40Z4 |
|
SOC_MKW41Z4 |
|
ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385) |
|
ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) |
|
MSP432P401R |
|
Nios IIf - Zephyr Golden Configuration |
|
Nios II - Experimental QEMU emulation |
|
NPCX7M6FB |
|
NRF51822_QFAA |
|
NRF51822_QFAB |
|
NRF51822_QFAC |
|
NRF52805_CAAA |
|
NRF52810_QFAA |
|
NRF52811_QFAA |
|
NRF52820_QDAA |
|
NRF52832_CIAA |
|
NRF52832_QFAA |
|
NRF52832_QFAB |
|
NRF52833_QIAA |
|
NRF52840_QIAA |
|
NRF5340_CPUAPP_QKAA |
|
NRF5340_CPUNET_QKAA |
|
NRF9160_SICA |
|
Synopsys nSIM simulator for ARC cores |
|
Synopsys ARC EM in nSIM |
|
Synopsys ARC EM7D_V22 in nSIM |
|
Synopsys ARC HS in nSIM |
|
Multi-core Synopsys ARC HS in nSIM |
|
Synopsys ARC SEM in nSIM |
|
OpenISA RV32M1 RI5CY core |
|
Enable support for OpenISA RV32M1 RISC-V processors. Choose this option to target the RI5CY or ZERO-RISCY core. This option should not be used to target either Arm core. |
|
OpenISA RV32M1 ZERO-RISCY core |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
CY8C6247BZI_D54 |
|
CY8C6347BZI_BLD53 |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
SAM3X4C |
|
SAM3X4E |
|
SAM3X8C |
|
SAM3X8E |
|
SAM3X8H |
|
SAM4E16C |
|
SAM4E16E |
|
SAM4E8C |
|
SAM4E8E |
|
SAM4LC2A |
|
SAM4LC2B |
|
SAM4LC2C |
|
SAM4LC4A |
|
SAM4LC4B |
|
SAM4LC4C |
|
SAM4LC8A |
|
SAM4LC8B |
|
SAM4LC8C |
|
SAM4LS2A |
|
SAM4LS2B |
|
SAM4LS2C |
|
SAM4LS4A |
|
SAM4LS4B |
|
SAM4LS4C |
|
SAM4LS8A |
|
SAM4LS8B |
|
SAM4LS8C |
|
SAM4S16B |
|
SAM4S16C |
|
SAM4S2A |
|
SAM4S2B |
|
SAM4S2C |
|
SAM4S4A |
|
SAM4S4B |
|
SAM4S4C |
|
SAM4S8B |
|
SAM4S8C |
|
SAMD20E14 |
|
SAMD20E15 |
|
SAMD20E16 |
|
SAMD20E17 |
|
SAMD20E18 |
|
SAMD20G14 |
|
SAMD20G15 |
|
SAMD20G16 |
|
SAMD20G17 |
|
SAMD20G17U |
|
SAMD20G18 |
|
SAMD20G18U |
|
SAMD20J14 |
|
SAMD20J15 |
|
SAMD20J16 |
|
SAMD20J17 |
|
SAMD20J18 |
|
SAMD21E15A |
|
SAMD21E16A |
|
SAMD21E17A |
|
SAMD21E18A |
|
SAMD21G15A |
|
SAMD21G16A |
|
SAMD21G17A |
|
SAMD21G17AU |
|
SAMD21G18A |
|
SAMD21G18AU |
|
SAMD21J15A |
|
SAMD21J16A |
|
SAMD21J17A |
|
SAMD21J18A |
|
SAMD51G18A |
|
SAMD51G19A |
|
SAMD51J18A |
|
SAMD51J19A |
|
SAMD51J20A |
|
SAMD51N19A |
|
SAMD51N20A |
|
SAMD51P19A |
|
SAMD51P20A |
|
SAME51J18A |
|
SAME51J19A |
|
SAME51J20A |
|
SAME51N19A |
|
SAME51N20A |
|
SAME53J18A |
|
SAME53J19A |
|
SAME53J20A |
|
SAME53N19A |
|
SAME53N20A |
|
SAME54N19A |
|
SAME54N20A |
|
SAME54P19A |
|
SAME54P20A |
|
SAME70J19 |
|
SAME70J19B |
|
SAME70J20 |
|
SAME70J20B |
|
SAME70J21 |
|
SAME70J21B |
|
SAME70N19 |
|
SAME70N19B |
|
SAME70N20 |
|
SAME70N20B |
|
SAME70N21 |
|
SAME70N21B |
|
SAME70Q19 |
|
SAME70Q19B |
|
SAME70Q20 |
|
SAME70Q20B |
|
SAME70Q21 |
|
SAME70Q21B |
|
SAMR21E16A |
|
SAMR21E17A |
|
SAMR21E18A |
|
SAMR21E19A |
|
SAMR21G16A |
|
SAMR21G17A |
|
SAMR21G18A |
|
SAMV71J19 |
|
SAMV71J19B |
|
SAMV71J20 |
|
SAMV71J20B |
|
SAMV71J21 |
|
SAMV71J21B |
|
SAMV71N19 |
|
SAMV71N19B |
|
SAMV71N20 |
|
SAMV71N20B |
|
SAMV71N21 |
|
SAMV71N21B |
|
SAMV71Q19 |
|
SAMV71Q19B |
|
SAMV71Q20 |
|
SAMV71Q20B |
|
SAMV71Q21 |
|
SAMV71Q21B |
|
This string holds the full part number of the SoC. It is a hidden option that you should not set directly. The part number selection choice defines the default value for this string. |
|
SOC for to the POSIX arch. It emulates a CPU running at an infinitely fast clock. That means the CPU will always run in zero time until completion after each wake reason (e.g. interrupts), before going back to idle. Note that an infinite loop in the code which does not sleep the CPU will cause the process to appear “hung”, as simulated time does not advance while the CPU does not sleep. Therefore do not use busy waits while waiting for something to happen (if needed use k_busy_wait()). Note that the interrupt handling is provided by the board. |
|
MEC1501 Power Management |
|
SOC_PSOC6_M0 |
|
SOC_PSOC6_M4 |
|
QEMU emulation of ARC cores |
|
Synopsys ARC EM in QEMU |
|
Synopsys ARC HS in QEMU |
|
QEMU virt platform (cortex-a53) |
|
LiteX VexRiscv system implementation |
|
Microsemi Mi-V system implementation |
|
SiFive Freedom SOC implementation |
|
QEMU RISC-V VirtIO Board |
|
SoC series name which can be found under soc/<arch>/<family>/<series>. This option holds the directory name used by the build system to locate the correct linker and header files. |
|
Enable support for the ARM DesignStart SoC Series |
|
Enable support for Beetle MCU Series |
|
Enable support for TI SimpleLink CC13x2 / CC26x2 SoCs |
|
Enable support for TI SimpleLink CC32xx |
|
Enable support for EFM32 GiantGecko MCU series |
|
Enable support for EFM32 Happy Gecko MCU series |
|
Enable support for EFM32 JadeGecko MCU series |
|
Enable support for EFM32 PearlGecko MCU series |
|
Enable support for EFM32 PearlGecko MCU series |
|
Enable support for EFM32 WonderGecko MCU series |
|
Enable support for EFR32BG13P Blue Gecko MCU series |
|
Enable support for EFR32 FlexGecko MCU series |
|
Enable support for EFR32 Mighty Gecko MCU series |
|
Enable support for EFR32MG21 Mighty Gecko MCU series |
|
Enable support for i.MX7 M4 MCU series |
|
Enable support for i.MX8MM M4 MCU series |
|
Enable support for M4 core of i.MX 6SoloX MCU series |
|
Enable support for i.MX RT MCU series |
|
Enable support for i.MX RT6XX Series MCU series |
|
Intel CAVS v1.5 |
|
Intel CAVS v1.8 |
|
Intel CAVS v2.0 |
|
Intel CAVS v2.5 |
|
Enable support for Kinetis K2x MCU series |
|
Enable support for Kinetis K6x MCU series |
|
Enable support for Kinetis K8x MCU series |
|
Enable support for Kinetis KE1xF MCU series |
|
Enable support for Kinetis KL2x MCU series |
|
Enable support for Kinetis KV5x MCU series |
|
Enable support for Kinetis KWx MCU series |
|
Enable support for LPC LPC11U6X MCU series |
|
Enable support for LPC LPC54XXX MCU series |
|
Enable support for LPC5500 Series MCU series |
|
Enable support for NUVOTON M48X MCU series |
|
Enable support for Microchip MEC Cortex-M4 MCU series |
|
Enable support for Microchip MEC Cortex-M4 MCU series |
|
Enable support for ARM MPS2 MCU Series |
|
Enable support for TI SimpleLink MSP432P4XX. |
|
Enable support for ARM MPS2 MCU Series |
|
Enable support for arm V2M Musca B1 MCU Series |
|
Enable support for Arm V2M Musca-S1 MCU Series |
|
Enable support for Nuvoton NPCX7 series |
|
Enable support for NRF51 MCU series |
|
Enable support for NRF52 MCU series |
|
Enable support for NRF53 MCU series |
|
Enable support for NRF91 MCU series |
|
Enable support for Cypress PSoC6 MCU series |
|
Enable support for Cypress PSoC6-BLE MCU series |
|
Enable support for ITE IT8XXX2 |
|
Enable support for Microsemi Mi-V |
|
Enable support for SiFive Freedom SOC |
|
QEMU RISC-V VirtIO Board |
|
Enable support for Atmel SAM3X Cortex-M3 microcontrollers. Part No.: SAM3X8E |
|
Enable support for Atmel SAM4E Cortex-M4 microcontrollers. Part No.: SAM4E16E, SAM4E16C, SAM4E8E, SAM4E8C |
|
Enable support for Atmel SAM4L Cortex-M4 microcontrollers. Part No.: SAM4LS8C, SAM4LS8B, SAM4LS8A, SAM4LS4C, SAM4LS4B, SAM4LS4A, SAM4LS2C, SAM4LS2B, SAM4LS2A, SAM4LC8C, SAM4LC8B, SAM4LC8A, SAM4LC4C, SAM4LC4B, SAM4LC4A SAM4LC2C, SAM4LC2B, SAM4LC2A |
|
Enable support for Atmel SAM4S Cortex-M4 microcontrollers. Part No.: SAM4S16C, SAM4S16B, SAM4S8C, SAM4S8B, SAM4S4C, SAM4S4B, SAM4S4A, SAM4S2C, SAM4S2B, SAM4S2A |
|
Enable support for Atmel SAMD20 Cortex-M0+ microcontrollers. |
|
Enable support for Atmel SAMD21 Cortex-M0+ microcontrollers. |
|
Enable support for Atmel SAMD51 Cortex-M4F microcontrollers. |
|
Enable support for Atmel SAME51 Cortex-M4F microcontrollers. |
|
Enable support for Atmel SAME53 Cortex-M4F microcontrollers. |
|
Enable support for Atmel SAME54 Cortex-M4F microcontrollers. |
|
Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers. Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20, SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B, SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B, SAME70Q20B, SAME70Q21B |
|
Enable support for Atmel SAMR21 Cortex-M0+ microcontrollers. |
|
Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers. Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20, SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B, SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B, SAMV71Q20B, SAMV71Q21B |
|
Enable support for STM32F0 MCU series |
|
Enable support for STM32F1 MCU series |
|
Enable support for stm32f2 MCU series |
|
Enable support for STM32F3 MCU series |
|
Enable support for STM32F4 MCU series |
|
Enable support for STM32F7 MCU series |
|
Enable support for STM32G0 MCU series |
|
Enable support for STM32G4 MCU series |
|
Enable support for STM32H7 MCU series |
|
Enable support for STM32L0 MCU series |
|
Enable support for STM32L1 MCU series |
|
Enable support for STM32L4 MCU series |
|
Enable support for STM32L5 MCU series |
|
Enable support for STM32MP1 MPU series |
|
Enable support for STM32WB MCU series |
|
Enable support for Broadcom Valkyrie Series |
|
Enable support for Broadcom Viper Series. |
|
Enable support for XMC 4xxx MCU series |
|
STM32F030X4 |
|
STM32F030X8 |
|
STM32F030XC |
|
STM32F051X8 |
|
STM32F070XB |
|
STM32F072XB |
|
STM32F091XC |
|
STM32F098XX |
|
STM32F100XB |
|
STM32F100XE |
|
STM32F103X8 |
|
STM32F103XB |
|
STM32F103XE |
|
STM32F105XC |
|
STM32F107XC |
|
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. They are intended for applications where connectivity and real-time performances are required such as industrial control, control panels for security applications, UPS or home audio. For STM32F107xx also the Ethernet MAC is available. |
|
|
|
STM32F207XX |
|
STM32F302X8 |
|
STM32F303X8 |
|
STM32F303XC |
|
STM32F303XE |
|
STM32F334X8 |
|
STM32F373XC |
|
STM32F401XC |
|
STM32F401XE |
|
STM32F405XG |
|
STM32F407XE |
|
STM32F407XG |
|
STM32F410RX |
|
STM32F411XE |
|
STM32F412CG |
|
STM32F412ZG |
|
STM32F413XX |
|
STM32F415XX |
|
STM32F417XX |
|
STM32F427XI |
|
STM32F429XI |
|
STM32F437XX |
|
STM32F446XX |
|
STM32F469XX |
|
STM32F723XX |
|
STM32F745XX |
|
STM32F746XX |
|
STM32F756XX |
|
STM32F767XX |
|
STM32F769XX |
|
STM32G031XX |
|
STM32G070XX |
|
STM32G071XX |
|
STM32G431XX |
|
STM32G474XX |
|
STM32H723XX |
|
STM32H743XX |
|
STM32H745XX |
|
STM32H747XX |
|
STM32H750XX |
|
STM32H753XX |
|
STM32L011XX |
|
STM32L031XX |
|
STM32L053XX |
|
STM32L071XX |
|
STM32L072XX |
|
STM32L073XX |
|
STM32L151X8A |
|
STM32L151XB |
|
STM32L151XBA |
|
STM32L151XC |
|
STM32L152XC |
|
STM32L152XE |
|
STM32L422XX |
|
STM32L432XX |
|
STM32L433XX |
|
STM32L452XX |
|
STM32L462XX |
|
STM32L471XX |
|
STM32L475XX |
|
STM32L476X |
|
STM32L496XX |
|
STM32L4R5XX |
|
STM32L4R9XX |
|
STM32L4S5XX |
|
STM32L552XX |
|
STM32L562XX |
|
STM32MP15_M4 |
|
STM32WB55XX |
|
TI LM3S6965 |
|
ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA |
|
ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-B1 |
|
ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-S1 |
|
Xen virtual machine on aarch64 |
|
Xilinx ZynqMP RPU |
|
SOC_XMC4500 |
|
Xtensa sample_controller core |
|
Use CASA atomic instructions. Defined by SPARC V9 and available in some LEON processors. |
|
Number of implemented register windows. |
|
Enable support for the SPI hardware bus. |
|
Enable support for the TI SimpleLink CC13xx / CC26xx SPI peripheral |
|
Corresponds to the SSI_TX_FIFO_DEPTH and SSI_RX_FIFO_DEPTH of the DesignWare Synchronous Serial Interface. Depth ranges from 2-256. |
|
Enable the SPI peripherals on Gecko |
|
Enable support for mcux spi driver. |
|
Enable support for mcux flexcomm spi driver. |
|
Enable support for mcux spi driver. |
|
Enable the RV32M1 LPSPI driver. |
|
Enable support for the SAM SPI driver. |
|
Enable support for the SAM0 SERCOM SPI driver. |
|
Enable SPI support on the STM32 family of processors. |
|
Enable support for the Microchip XEC QMSPI driver. |
|
Enable Dual Core |
|
This module implements a kernel device driver for the LowPower Timer and provides the standard “system clock driver” interfaces. |
|
Set the board system oscillator settling time in us. This should be set by the board’s defconfig. |
|
This option specifies hardware clock. |
|
This option specifies the nominal frequency of the system clock in Hz. For asynchronous timekeeping, the kernel defines a “ticks” concept. A “tick” is the internal count in which the kernel does all its internal uptime and timeout bookeeping. Interrupts are expected to be delivered on tick boundaries to the extent practical, and no fractional ticks are tracked. The choice of tick rate is configurable by this option. Also the number of cycles per tick should be chosen so that 1 millisecond is exactly represented by an integral number of ticks. Defaults on most hardware platforms (ones that support setting arbitrary interrupt timeouts) are expected to be in the range of 10 kHz, with software emulation platforms and legacy drivers using a more traditional 100 Hz value. Note that when available and enabled, in “tickless” mode this config variable specifies the minimum available timing granularity, not necessarily the number or frequency of interrupts delivered to the kernel. A value of 0 completely disables timer support in the kernel. |
|
Option which implements default policy of enabling logging in minimal mode for all test cases. For tests that need alternate logging configuration, or no logging at all, disable this in the project-level defconfig. |
|
This option enables the TinyCrypt cryptography library. |
|
Enable the TI SimpleLink CC13xx / CC26xx UART driver. |
|
This option specifies the name of UART device to be used for UART console. |
|
Enable the Gecko uart driver. |
|
This option enables the UART driver for NXP i.MX7 family processors. |
|
This option enables interrupt support for UART allowing console input and other UART based drivers. |
|
Enable UART driver for LPC11U6X series |
|
Enable the MCUX uart driver. |
|
Enable the MCUX USART driver. |
|
Enable the MCUX IUART driver. |
|
Enable the MCUX LPSCI driver. |
|
Enable the MCUX LPUART driver. |
|
Enable support for NPCX UART driver. |
|
This option enables the NS16550 serial driver. This driver can be used for the serial hardware available on x86 boards. |
|
In some case, e.g. ARC HS Development kit, the peripheral space of ns 16550 (DesignWare UART) only allows word access, byte access will raise exception. |
|
The maximum number of supported driver instances in device tree. |
|
This option specifies the name of UART device to be used for pipe UART. |
|
This option enables the UART driver for the PL011 |
|
Build the driver to utilize UART controller Port 0. |
|
Build the driver to utilize UART controller Port 1. |
|
This option enables the UART driver for PSoC6 family of processors. |
|
Enable the RV32M1 LPUART driver. |
|
This option enables the SERCOMx USART driver for Atmel SAM0 MCUs. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This tells the driver to configure the UART port at boot, depending on the additional configure options below. |
|
This option enables the UART driver for STM32 family of processors. Say y if you wish to use serial port on STM32 MCU. |
|
This option enables the XMC4XX UART driver, for UART_0. |
|
This option enables the USARTx driver for Atmel SAM MCUs. |
|
Kinetis and RT EHCI USB Device Controller Driver. |
|
SAM family USB HS device controller Driver. |
|
SAM0 family USB device controller Driver. |
|
Enable USB support on the STM32 F0, F1, F2, F3, F4, F7, L0, L4 and G4 family of processors. |
|
Kinetis USB Device Controller Driver. |
|
NXP MCUX CMOS Sensor Interface (CSI) driver |
|
Include support for watchdogs. |
|
Keep the watchdog timer enabled at boot with the internal 128kHz LPO clock (and a prescaler of 256) as clock source. The application can take over control of the watchdog timer after boot and install a different timeout, if needed. |
|
This processor enables the watchdog timer with a short window for configuration upon reset. Therefore, this requires that the watchdog be configured during reset handling. |
|
Initial timeout value for the watchdog timer in milliseconds. |
|
Enable the mcux imx wdog driver. |
|
Enable the mcux wdog driver. |
|
Enable the mcux wdog32 driver. |
|
Enable the mcux wwdt driver. |
|
Enable support for NPCX Watchdog driver. Besides watchdog functionality, it also provides the protection mechanism over software execution. After setting the configuration registers, the software can lock it to provide a higher level of protection against subsequent erroneous software action. Once a section of the TWD is locked, only reset or the unlock sequence releases it. |
|
Enable WDT driver for Atmel SAM0 MCUs. |
|
Installing interrupt handlers with irq_connect_dynamic() requires some stub code to be generated at build time, one stub per dynamic interrupt. |
|
This option allows the kernel to operate with its text and read-only sections residing in ROM (or similar read-only memory). Not all boards support this option so it must be used with care; you must also supply a linker command file when building your image. Enabling this option increases both the code and data footprint of the image. |
|
Set the external oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
Specify which special register to store the pointer to _kernel.cpus[] for the current CPU. |
|
Enables a system timer driver for Xtensa based on the CCOUNT and CCOMPARE special registers. |
|
Test function thread stack size |