Zephyr Boards Configuration Options¶
Kconfig files describe build-time configuration options (called symbols
in Kconfig-speak), how they’re grouped into menus and sub-menus, and
dependencies between them that determine what configurations are valid.
Kconfig files appear throughout the directory tree. For example,
subsys/power/Kconfig defines power-related options.
This documentation is generated automatically from the Kconfig files by
the gen_kconfig_rest.py script. Click on symbols for more
information.
Configuration Options¶
Symbol name |
Help/prompt |
|---|---|
This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 2nd level interrupt ISRs begins. This is typically allocated after ISRs for level 1 interrupts. |
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This is the level $(prev-level-num) interrupt number for level $(cur-level-num) interrupt aggregator $(aggregator). |
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This is the offset in _sw_isr_table, the generated ISR handler table, where storage for 3rd level interrupt ISRs begins. This is typically allocated after ISRs for level 2 interrupts. |
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Enable LMP90xxx ADC driver. The LMP90xxx is a multi-channel, low power sensor analog frontend (AFE). |
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Enable GPIO child device support in the LMP90xxx ADC driver. The GPIO functionality is handled by the LMP90xxx GPIO driver. |
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Enable MCP3204/MCP3208 ADC driver. The MCP3204/MCP3208 are 4/8 channel 12-bit A/D converters with SPI interface. |
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Enable Audio Codec Driver Configuration |
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Enable Digital Microphone Driver Configuration |
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Enable Intel digital PDM microphone driver |
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Enable TLV320DAC support on the selected board |
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Enable the battery sense circuit |
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This option holds the name of the board and is used to locate the files related to the board in the source tree (under boards/). The Board is the first location where we search for a linker.ld file, if not found we look for the linker file in soc/<arch>/<family>/<series> |
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96Boards AEROCORE2 (STM32F427) |
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96Boards Argonkey |
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96Boards Avenger96 Board |
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96Boards Carbon (STM32F401) |
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96Boards Carbon (nRF51) |
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96Boards Meerkat96 board |
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96Boards Neonkey |
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96Boards Nitrogen |
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96Boards STM32 Sensor Mezzanine Board |
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96boards WisTrio Development Board |
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ACRN User OS |
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Actinius Icarus |
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Actinius Icarus Non-Secure |
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Adafruit Feather M0 Basic Proto |
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Adafruit Feather nRF52840 Express |
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Feather STM32F405 Express Board |
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Adafruit ItsyBitsy M4 Express |
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Adafruit Trinket M0 |
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Altera MAX10 Board |
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Arduino Due Board |
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Arduino Nano 33 BLE board |
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Sends the console output over the USB port |
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Initializes the internal I2C sensors on the board |
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Arduino Nano 33 IOT |
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Arduino Zero |
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Digilent Arty A7 ARM DesignStart Cortex-M1 |
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Digilent Arty A7 ARM DesignStart Cortex-M3 |
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SAM D20 Xplained Pro |
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SAM D21 Xplained Pro |
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SAM E54 Xplained Pro |
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SAM R21 Xplained Pro |
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BBC MICRO:BIT |
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BBC MICRO:BIT_V2 |
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Broadcom Viper BCM958402M2_A72 |
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Broadcom Viper BCM958402M2_M7 |
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BL652 DVK |
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BL653 DVK |
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BL654 DVK |
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WeAct Studio Black Pill V3.0+ Board |
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WeAct Studio Black Pill V2.0+ Board |
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Black F407VE Development Board |
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Black F407ZG Pro Development Board |
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BT510 |
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STMicroelectronics B-L072Z-LRWAN1 Discovery kit |
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STM32L4S5I IOT Discovery kit |
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TI CC1352R1 LaunchXL |
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TI CC1352R SensorTag |
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TI CC26x2R1 LaunchXL |
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TI CC3220SF LAUNCHXL |
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TI CC3235SF LAUNCHXL |
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Initialization priority for the CCS_VDD power rail. This powers the CCS811 gas sensor. The value has to be greater than BOARD_VDD_PWR_CTRL_INIT_PRIORITY, but smaller than SENSOR_INIT_PRIORITY. |
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Circuit Dojo nRF9160 Feather |
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Circuit Dojo nRF9160 Feather non-secure |
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Toradex Colibri iMX7 Dual |
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nRF52840 based Advanced BLE Cell |
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PSoC6 BLE Pioneer Kit [M0 CPU0] |
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PSoC6 BLE Pioneer Kit [M4 CPU1] |
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PSoC6 WiFi-BT Pioneer Kit M0 |
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PSoC6 WiFi-BT Pioneer Kit M4 |
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Decawave DWM1001-DEV |
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DEGU_EVK |
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This hidden option is set in the board configuration and indicates the Zephyr release that the board configuration will be removed. When set, any build for that board will generate a clearly visible deprecation warning. |
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Discovery IoT L475 Development Board |
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Dragino LSN50 Sensor Node |
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SiLabs EFM32GG-SLWSTK6121A (WGM160P) |
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SiLabs EFM32GG-STK3701A (Giant Gecko 11) |
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SiLabs EFM32HG-SLSTK3400A (Happy Gecko) |
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SiLabs EFM32PG-STK3401A (Pearl Gecko) |
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SiLabs EFM32PG-STK3402A (Pearl Gecko) |
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SiLabs EFM32PG-STK3402A (Jade Gecko) |
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SiLabs EFM32WG-STK3800 (Wonder Gecko) |
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SiLabs EFR32MG-SLTB004A (Thunderboard Sense 2) |
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Silicon Labs BRD4104A (Blue Gecko Radio Board) |
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Silicon Labs BRD4180A (Mighty Gecko Radio Board) |
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Silicon Labs BRD4250B (Flex Gecko Radio Board) |
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Elkhart Lake CRB |
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Elkhart Lake CRB (with Slim Bootloader) |
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The ARC EM Software Development Platform (emsdp) is an FPGA based development platform intended to support ARC licenses in developing their software for the ARC EM processor family and ARC EM Subsystems. It has the support for ARC EM4, EM5D, EM6, EM7D, EM9D and EM11D processors. ARC EM Enhanced Security Package (ESP) and ARC EM Subsystems (DFSS, SCSS, DSS) are also supported. |
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The DesignWare ARC EM Starter Kit board is a board that can host up to 3 different SOC FPGA bit files. Both version 2.2 and 2.3 firmware have EM7D, EM9D and EM11D configurations. EM9D using CCM memories and is a Harvard Architecture. EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache. EM7D of EMSK 2.3 supports secure mode. |
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2.2 |
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2.3 |
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This option enables releasing the Network ‘force off’ signal, which as a consequence will power up the Network MCU during system boot. Additionally, the option allocates GPIO pins that will be used by UARTE of the Network MCU. Note: GPIO pin allocation can only be configured by the secure Application MCU firmware, so when this option is used with the non-secure version of the board, the application needs to take into consideration, that the secure firmware image must already have configured GPIO allocation for the Network MCU. |
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Enable DCDC mode |
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Enable Application MCU DCDC converter |
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Enable High Voltage DCDC converter |
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Enable Network MCU DCDC converter |
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ESP32 Development Board |
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Seagate FireCuda Gaming SSD (FaZe) |
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NXP FRDM-K22F |
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Freescale FRDM-K64F |
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NXP FRDM-K82F |
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NXP FRDM-KL25Z |
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NXP FRDM-KW41Z |
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Generic LEON3 system |
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This is the EC (Embedded Controller) inside a Lenovo Chromebook Duet and 10e Chromebook Tablet. The EC handles battery charging, keyboard scanning, USB Power Delivery and sensors. So far for Zephyr only a simple serial console and I2C are supported. |
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GR716-MINI Development Board |
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If selected, applications are linked so that they can be loaded by Nordic nRF5 bootloader. |
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Should be selected if board provides custom method for retrieving timestamps and cycle count. |
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NXP Hexiwear K64 |
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Hexiwear KW40Z |
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HiFive1 target |
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HiFive1 Rev B target |
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Holyiot YJ-16019 |
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The DesignWare ARC HS Development Kit is a ready-to-use platform for rapid software development on the ARC HS3x family of processors. It supports single- and multi-core ARC HS34, HS36 and HS38 processors and offers a wide range of interfaces |
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Board initialization priority. The board initialization must take place after the GPIO driver is initialized. |
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Intel ADSP CAVS 1.5 |
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Intel ADSP CAVS 1.8 |
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Intel ADSP CAVS 2.0 |
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Intel ADSP CAVS 2.5 |
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Xtensa on Intel_S1000 |
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The DesignWare ARC IoT Development Kit board is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. It includes a silicon implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC’s 55-nm ultra-low power process, and a rich set of peripherals commonly used in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO and ADCs. |
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Segger IP-K66F |
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IT8XXX2 EV-board |
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Board with LiteX/VexRiscV CPU |
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NXP LPCXPRESSO-11U68 |
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NXP LPCXPRESSO-54114 M0 |
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NXP LPCXPRESSO-54114 M4 |
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NXP LPCXPRESSO-55S16 |
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NXP LPCXPRESSO-55S28 |
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NXP LPCXPRESSO-55S69 [CPU0] |
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NXP LPCXPRESSO-55S69 [CPU1] |
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Microsemi M2GL025 IGLOO2 dev board with Mi-V CPU |
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Microchip MEC1501 Modular ASSY 6885 Development board |
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Microchip MEC15XX EVB ASSY 6853 Development board |
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Microchip MEC2016 EVB ASSY 6797 Development board |
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Mercury XU Board |
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MikroE Clicker 2 for STM32 board |
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Mikroe MINI-M4 for STM32 Board |
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NXP i.MX8M Mini EVK |
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NXP MIMXRT1010-EVK |
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NXP MIMXRT1015-EVK |
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NXP MIMXRT1020-EVK |
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NXP MIMXRT1024-EVK |
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NXP MIMXRT1050-EVK |
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NXP MIMXRT1050-EVK-QSPI |
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NXP MIMXRT1060-EVK |
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NXP MIMXRT1060-EVK-HYPERFLASH |
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NXP MIMXRT1064-EVK |
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NXP MIMXRT685-EVK |
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MinnowBoard Max |
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MM MM-SWIFTIO |
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ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385) |
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ARM Cortex-M33 SMM on V2M-MPS2 (AN521) |
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TI MSP-EXP432P401R LAUNCHXL |
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ARM Cortex-M33 SMM on V2M-MUSCA |
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ARM Cortex-M33 SMM on V2M-MUSCA |
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ARM Cortex-M33 SMM on V2M-MUSCA-S1 |
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Will produce a console Linux process which can be executed natively as a 32-bit executable. It provides some minimal needed models: An interrupt controller, timer (system tick), and redirects kernel prints to stdout. |
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Will produce a console Linux process which can be executed natively as a 64-bit executable. It provides some minimal needed models: An interrupt controller, timer (system tick), and redirects kernel prints to stdout. |
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Nuvoton NPCX7M6FB EVB Development board |
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nRF21540 DK NRF52840 |
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nRF51 DK NRF51422 |
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nRF51 Dongle NRF51422 |
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nRF51 BLE400 |
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nRF51 BLENANO |
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nRF51 VBLUno51 BLE |
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nRF52832-MDK |
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nRF52833 DK NRF52820 |
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NRF52833 DK NRF52833 |
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nRF52840 DK NRF52811 |
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nRF52840 DK NRF52840 |
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nRF52840 DONGLE NRF52840 |
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Electronut Labs Blip |
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Use a GPIO pin to reset the nRF52840 controller and let it wait until all bytes traveling to the H4 device have been received and drained, thus ensuring communication can begin correctly. |
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GPIO pin on the nRF9160 used to reset the nRF52840. |
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NRF52840-MDK |
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NRF52840 PAPYR |
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nRF52 DK NRF52805 |
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nRF52 DK NRF52810 |
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nRF52 DK NRF52832 |
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nRF52 ADAFRUIT FEATHER |
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nRF52 BLENANO2 |
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Will produce a console Linux process which can be executed natively. It needs the BabbleSim simulator both in compile time and to execute |
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nRF52 SPARKFUN |
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nRF52 VBLUno52 |
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nRF5340 DK nRF5340 Application MCU |
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nRF5340 DK nRF5340 Application MCU non-secure |
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nRF5340 DK NRF5340 Network MCU |
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nRF5340 PDK nRF5340 Application MCU |
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nRF5340 PDK nRF5340 Application MCU non-secure |
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nRF5340 PDK NRF5340 Network MCU |
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Route to Arduino pins |
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Route to buttons on the kit |
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Route to Arduino pins |
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Route to buttons on the kit |
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Pin 0: nRF9160 P0.17 connects to A3 Pin 1: nRF9160 P0.18 connects to A4 Pin 2: nRF9160 P0.19 connects to A5 |
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This connects the following pins on the nRF9160 to pins on the nRF52840: Pin 0: nRF9160 P0.17 connects to nRF52840 P0.17 Pin 1: nRF9160 P0.18 connects to nRF52840 P0.20 Pin 2: nRF9160 P0.19 connects to nRF52840 P0.15 |
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Pin 3: nRF9160 P0.21 connects to nRF52840 P0.22 Pin 4: nRF9160 P0.22 connects to nRF52840 P1.04 Pin 5: nRF9160 P0.23 connects to nRF52840 P1.02 |
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Pin 3: nRF9160 P0.21 connects to TRACECLK Pin 4: nRF9160 P0.22 connects to TRACEDATA0 Pin 5: nRF9160 P0.23 connects to TRACEDATA1 |
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Pin 6: nRF9160 COEX0 connects to COEX0_PH Pin 7: nRF9160 COEX1 connects to COEX1_PH Pin 8: nRF9160 COEX2 connects to COEX2_PH |
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Pin 6: nRF9160 COEX0 connects to nRF52840 P1.13 Pin 7: nRF9160 COEX1 connects to nRF52840 P1.11 Pin 8: nRF9160 COEX2 connects to nRF52840 P1.15 |
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Route to Arduino pins |
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Route to LED on the kit |
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Route to Arduino pins |
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Route to LED on the kit |
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Route to Arduino pins |
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Route to LED on the kit |
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Route to Arduino pins |
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Route to LED on the kit |
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NRF9160 DK NRF52840 |
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Let the nRF52840 be reset from the nRF9160 via a GPIO line. The GPIO line may only be one of the first 6 MCU interface pins. The line is active high. |
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Pin P0.15 on nRF52840, connected to P0.19 on the nRF9160. |
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Pin P0.17 on nRF52840, connected to P0.17 on the nRF9160. |
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Pin P0.20 on nRF52840, connected to P0.18 on the nRF9160. |
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Pin P0.22 on nRF52840, connected to P0.21 on the nRF9160. |
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Pin P1.02 on nRF52840, connected to P0.23 on the nRF9160. |
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Pin P1.04 on nRF52840, connected to P0.22 on the nRF9160. |
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nRF9160 DK NRF9160 |
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nRF9160 DK NRF9160 non-secure |
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Route to Arduino pins |
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Route to switches on the kit |
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Route to Arduino pins |
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Route to switches on the kit |
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Route to Arduino pins |
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Route to VCOM0 |
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Route to Arduino pins |
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Route to VCOM2 |
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nRF9160 innblue v2.1 |
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nRF9160 innblue v2.1 non-secure |
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nRF9160 innblue v2.2 |
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nRF9160 innblue V2.2 non-secure |
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The DesignWare ARC nSIM board is a virtual board based on the ARC nSIM simulator. It demonstrates the ARC core features and a console based on the ns16550 UART model. |
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NUCLEO-64 F030R8 Development Board |
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NUCLEO-64 F070RB Development Board |
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NUCLEO-64 F091RC Development Board |
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NUCLEO-64 F103RB Development Board |
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NUCLEO-144 F207ZG Development Board |
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NUCLEO-64 F302R8 Development Board |
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NUCLEO-32 F303K8 Development Board |
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NUCLEO-64 F303RE Development Board |
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NUCLEO-64 F334R8 Development Board |
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NUCLEO-64 F401RE Development Board |
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Nucleo F410RB Development Board |
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NUCLEO-64 F411RE Development Board |
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NUCLEO-144 F412ZG Development Board |
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NUCLEO-144 F413ZH Development Board |
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NUCLEO-144 F429ZI Development Board |
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Nucleo F446RE Development Board |
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Nucleo F746ZG Development Board |
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Nucleo F756ZG Development Board |
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Nucleo F767ZI Development Board |
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NUCLEO-64 G071RB Development Board |
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Nucleo G431RB Development Board |
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Nucleo G474RE Development Board |
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NUCLEO-H723ZG Development Board |
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Nucleo H743ZI Development Board |
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NUCLEO-H745ZI-Q Development Board |
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NUCLEO-H745ZI-Q Development Board |
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NUCLEO-32 L011K4 Development Board |
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NUCLEO-32 L031K6 Development Board |
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NUCLEO-64 L053R8 Development Board |
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NUCLEO-64 L073RZ Development Board |
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NUCLEO-64 L152RE Development Board |
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Nucleo L432KC Development Board |
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Nucleo L433RC-P Development Board |
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Nucleo L452RE Development Board |
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Nucleo L452RE-P Development Board |
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Nucleo L476RG Development Board |
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Nucleo L496ZG Development Board |
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Nucleo L4R5ZI Development Board |
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Nucleo L552ZE Q Development Board |
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Nucleo WB55RG Development Board |
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NUVOTON PFM MP487 Development Board |
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ODROID-GO Game Kit |
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OLIMEXINO-STM32 Development Board |
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OLIMEX-STM32-E407 Development Board |
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OLIMEX-STM32-H103 Development Board |
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OLIMEX-STM32-H407 Development Board |
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OLIMEX-STM32-P405 Development Board |
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Particle Argon Board |
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Particle Boron Board |
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Particle Xenon Board |
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Pico-PI iMX7D Dual |
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PineTime DevKit0 |
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Pinnacle 100 DVK |
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ARC QEMU for EM & HS cores |
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Cortex-A53 Emulation (QEMU) |
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Cortex-M0 Emulation (QEMU) |
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Cortex-M3 Emulation (QEMU) |
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Cortex-R5 Emulation (QEMU) |
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QEMU LEON3 target |
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QEMU NIOS II target |
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QEMU RISCV32 target |
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QEMU RISCV64 target |
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QEMU x86 |
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QEMU x86_64 |
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Xtensa emulation using QEMU |
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QuickLogic Quick Feather target |
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RAK5010 DK NRF52840 |
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reel board equipped with GDEH0213B1 display |
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reel board equipped with GDEH0213B72 display |
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Ruuvi-RuuviTag |
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RV32M1 RISC-V cores |
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Atmel SAM4E Xplained Pro |
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Atmel SAM4L-EK |
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Atmel SAM4S Xplained |
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Atmel SMART SAM E70 Xplained Board |
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Atmel SMART SAM V71 Xplained Ultra Board |
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Seeeduino XIAO |
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SEGGER STM32F407 Trace Reference Board |
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Use the external SIM for communication, instead of the eSIM |
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SensorTile.box Development Board |
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Serpente |
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STM32 Flight Controller Unit |
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STM3210C-EVAL Evaluation Board |
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STM32373C_EVAL Evaluation Board |
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STM32F030 DEMO Board |
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STM32F072B-DISCO Development Board |
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STM32F072-EVAL Development Board |
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STM32F0DISCOVERY Development Board |
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STM32F103RCT6 Mini Board |
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STM32F3DISCOVERY Development Board |
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STM32F411E-DISCO Development Board |
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STM32F412G-DISCO Development Board |
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STM32F429I-DISC1 Development Board |
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STM32F469I-DISCO Development Board |
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STM32F4DISCOVERY Development Board |
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STM32F723E Discovery Development Board |
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STM32F746G Discovery Development Board |
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STM32F769I Discovery Development Board |
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STM32G0316 Discovery Development Board |
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STM32H747I Discovery Development Board |
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STM32H747I Discovery Development Board |
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STM32L1DISCOVERY Development Board |
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STM32L476G Discovery Development Board |
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STM32L496G Discovery Development Board |
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STM32L562E-DK Discovery Development Board |
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STM32MP157C Discovery Development 2 Board |
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STM32VLDISCOVERY Development Board |
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STM32 Minimum Development Board (Black) |
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STM32 Minimum Development Board (Blue) |
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Thingy52 NRF52832 |
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NXP TWR-KE18F |
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Enable the CLKOUT signal on FlexIO header pin 7 (PTE10). |
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Use PTE6 as dedicated SPI_0 PCS2 chip select |
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Use PTD3 as dedicated SPI_1 PCS0 chip select |
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Use PTA16 as dedicated SPI_1 PCS2 chip select |
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NXP TWR-KV58F220M |
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UDOO Neo Full |
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UP Squared (x86_64) |
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UP Squared (x86) |
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NXP USB-KW24D512 |
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ARM V2M Beetle Board |
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Broadcom Valkyrie BCM958401M2 |
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Initialization priority for the VDD power rail. Has to be greater than GPIO_NRF_INIT_PRIORITY. |
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WaRP7 iMX7 Solo |
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Waveshare OPEN103Z Development Board |
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Xen Virtual Machine |
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Infineon Relax Kit |
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Xtensa Development ISS |
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Xtensa Development ISS |
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This option enables Bluetooth support. |
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Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS. |
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Select this for LE Central role support. |
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Enables support for SoC native controller implementations. |
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This option adds support for ECDH HCI commands. |
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This option is set by the Bluetooth controller to indicate support for the Zephyr HCI Vendor-Specific Commands and Event. |
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Enable support for throttling ACL buffers from the controller to the host. This is particularly useful when the host and controller are on separate cores since it ensures that we do not run out of incoming ACL buffers. |
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Enable support for the Zephyr HCI Vendor-Specific Extensions in the Host and/or Controller. This enables Write BD_ADDR, Read Build Info, Read Static Addresses and Read Key Hierarchy Roots vendor commands. |
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This option enables support for LE Connection oriented Channels, allowing the creation of dynamic L2CAP Channels. |
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Select this for LE Peripheral role support. |
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This option enables support for the Security Manager Protocol (SMP), making it possible to pair devices over LE. |
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Enable support for devices compatible with the BlueNRG Bluetooth Stack. Current driver supports: ST BLUENRG-MS. |
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Build a “raw” binary zephyr/zephyr.bin in the build directory. The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. |
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Build an ELF binary that can run in the host system at zephyr/zephyr.exe in the build directory. The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. |
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Build a stripped binary zephyr/zephyr.strip in the build directory. The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. |
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When enabled, this option instructs the Zephyr build process to additionaly generate a TF-M image for the Secure Execution environment, along with the Zephyr image. The Zephyr image itself is to be executed in the Non-Secure Processing Environment. The required dependency on TRUSTED_EXECUTION_NONSECURE ensures that the Zephyr image is built as a Non-Secure image. Both TF-M and Zephyr images, as well as the veneer object file that links them, are generated during the normal Zephyr build process.
|
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Enable MCP2515 CAN Driver |
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Parent interrupt number to which CAVS_0 maps |
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Parent interrupt number to which CAVS_1 maps |
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Parent interrupt number to which CAVS_2 maps |
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Parent interrupt number to which CAVS_3 maps |
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This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for CAVS Interrupt Controller are assigned. |
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D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler), allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
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APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16 |
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APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16 |
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APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16 |
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APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16 |
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hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512. |
|
Enable the low-speed external (LSE) clock supplied with a 32.768 kHz crystal resonator oscillator. |
|
Set the internal high frequency RC oscillator frequency in Hz. This should be set by the board’s defconfig. Only supported values may be used here. Setting this to 0, skips the configuration of the high frequency RC oscillator completely. This may be desired, if the bootloader already configured it properly or the device’s default clock source should be used with it’s default configuration. |
|
Set the external high frequency oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
Set the external low frequency oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
This value is used as a base value to retry pending CoAP packets. |
|
Enable counter driver based on RTCC module for Silicon Labs Gecko chips. |
|
This option is enabled when the CPU implements the SysTick timer. |
|
This option is enabled when the CPU has a Memory Protection Unit (MPU) in ARM flavor. |
|
Enable the driver for the TI DACx0508. |
|
File system on a SDHC card. |
|
File system on a SDHC card accessed over SPI. |
|
File system on a SDHC card accessed over USDHC instance 1. |
|
This is typically the minimum block size that is erased at one time in flash storage. Typically it is equal to the flash memory page size. |
|
Flash device name to be used as storage backend |
|
This is the start address alignment required by the flash component. |
|
This is the maximum number of bytes that the flash_write API can accept per invocation. API. |
|
This is start address of the flash to be used as storage backend. |
|
This is the file system volume size in bytes. |
|
DesignWare DMA driver. |
|
The board which will be used for CPUAPP domain when creating a multi image application where one or more images should be located on another board. |
|
The board which will be used for CPUNET domain when creating a multi image application where one or more images should be located on another board. For example hci_rpmsg on the nRF5340_cpunet for Bluetooth applications. |
|
Add support for KSZ8794 DSA device driver. |
|
Parent interrupt number to which DW_ICTL maps |
|
This indicates the offset in the SW_ISR_TABLE beginning from where the ISRs for Designware Interrupt Controller are assigned. |
|
Enable support for Atmel AT24 (and compatible) I2C EEPROMs. |
|
Enable Simulated EEPROM driver. |
|
This option enables the entropy number generator for ESP32 SoCs. With Wi-Fi and Bluetooth disabled, this will produce pseudo-entropy numbers: noise from these radios are used to feed entropy in this generator. |
|
Enables 8042 keyboard controller over eSPI peripheral channel. |
|
Enable the Microchip XEC ESPI driver. |
|
ENC28J60C Stand-Alone Ethernet Controller with SPI Interface |
|
Include port 0 driver |
|
ENC424J600C Stand-Alone Ethernet Controller with SPI Interface |
|
Enable Ethernet driver for Silicon Labs Gecko chips. |
|
Enable MCUX Ethernet driver. Note, this driver performs one shot PHY setup. There is no support for PHY disconnect, reconnect or configuration change. |
|
Some PHY devices, with DSA capabilities do not use SMI for communication with MAC ENET controller. Other busses - like SPI or I2C are used instead. |
|
Setting this option will configure MCUX clock block to feed RMII reference clock from external source (ENET_1588_CLKIN) |
|
Enable native posix ethernet driver. Note, this driver is run inside a process in your host system. |
|
Enable Atmel SAM MCU Family Ethernet driver. |
|
Device name, e.g. I2C_0, of an I2C bus driver device. It is required to obtain handle to the I2C device object. |
|
Read MAC address from an I2C EEPROM. |
|
Internal address of the EEPROM chip where the MAC address is stored. Chips with 1 to 4 byte internal address size are supported. Address size has to be configured in a separate Kconfig option. |
|
Size (in bytes) of the internal EEPROM address. |
|
I2C 7-bit address of the EEPROM chip. |
|
This option enables the test random number generator for the native_posix board (ARCH_POSIX). This is based on the host random() API. Note that this entropy generator is only meant for test purposes and does not generate real entropy. It actually generates always the same sequence of random numbers if initialized with the same seed. |
|
This option specifies the base address of the flash on the board. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration. |
|
This option is enabled when the SoC flash driver supports retrieving the layout of flash memory pages. |
|
This option specifies the byte offset from the beginning of flash that the kernel should be loaded into. Changing this value from zero will affect the Zephyr image’s link, and will decrease the total amount of flash available for use by application code. If unsure, leave at the default value 0. |
|
If non-zero, this option specifies the size, in bytes, of the flash area that the Zephyr image will be allowed to occupy. If zero, the image will be able to occupy from the FLASH_LOAD_OFFSET to the end of the device. If unsure, leave at the default value 0. |
|
MCUX FlexSPI NOR driver |
|
Enables API for retrieving the layout of flash memory pages. |
|
Enable the flash simulator. |
|
This option specifies the size of the flash in kB. It is normally set by the board’s defconfig file and the user should generally avoid modifying it via the menu configuration. |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Say Y to route data ready interrupt to INT1 pin. Say N to route to INT2 pin. |
|
Enable driver for GD7965 compatible controller. |
|
Include GPIO drivers in system config |
|
GPIO as pin reset (reset button) |
|
Enable config options to support the ARM CMSDK GPIO controllers. Says n if not sure. |
|
Enable driver for Designware GPIO |
|
Include Designware GPIO driver |
|
Include Designware GPIO driver |
|
Include Designware GPIO driver |
|
Include Designware GPIO driver |
|
Enable Port 0. |
|
Enable Port 1. |
|
Enable nRF GPIO port P1 config options. |
|
Enable support for the Atmel SAM ‘PORT’ GPIO controllers. |
|
Enable support for the Stellaris GPIO controllers. |
|
Enable Xilinx AXI GPIO v2 driver. |
|
This option is selected by targets having a FLASH_LOAD_OFFSET and FLASH_LOAD_SIZE. |
|
This option specifies that the target board has SDL support |
|
This option specifies the size of the heap memory pool used when dynamically allocating memory using k_malloc(). The maximum size of the memory pool is only limited to available memory. A size of zero means that no heap memory pool is defined. |
|
Select this option to enable hardware-based platform features to catch stack overflows when the system is running in privileged mode. If CONFIG_USERSPACE is not enabled, the system is always running in privileged mode. Note that this does not necessarily prevent corruption and assertions about the overall system state when a fault is triggered cannot be made. |
|
Enable I2C Driver Configuration |
|
Enable I2C Port 0 |
|
Enable I2C Port 1 |
|
Enable the CC32XX I2C driver. |
|
Enable the Design Ware I2C driver |
|
Set the clock speed for I2C |
|
Enable support for nrfx TWI drivers for nRF MCU series. |
|
Enable Atmel SAM MCU Family (TWI) I2C bus driver. |
|
I2C driver for ARM’s SBCon two-wire serial bus interface |
|
Enable I2C support on SiFive Freedom |
|
Enable Inter Sound (I2S) bus driver for Intel_S1000 based on Synchronous Serial Port (SSP) module. |
|
Division factor for the audio PLL (PLLI2S) VCO input clock. PLLM factor should be selected to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63 |
|
Multiply factor for the audio PLL (PLLI2S) VCO output clock. PLLN factor should be selected to ensure that the VCO output frequency ranges from 100 to 432 MHz. Allowed values: 50-432 |
|
Division factor for the I2S clock. PLLR factor should be selected to ensure that the I2S clock frequency is less than or equal to 192MHz. Allowed values: 2-7 |
|
Enable it if I2S clock should be provided by the PLLI2S. If not enabled the clock will be provided by HSI/HSE. |
|
Decawave DW1000 Driver support |
|
NXP MCR20A Driver support |
|
nRF52 series IEEE 802.15.4 Driver |
|
ATMEL RF2XX Driver support |
|
Enable driver for ILI9340 display driver. |
|
Enable driver for ILI9488 display driver. |
|
Enable support for Intel’s GMM and Neural Network Accelerator |
|
Each instance of the IPM console receiver driver creates a worker thread to print out incoming messages from the remote CPU. Specify the stack size for these threads here. |
|
Driver for SSE 200 MHU (Message Handling Unit) |
|
Enable IPM Message Channel 0 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Enable IPM Message Channel 1 |
|
IPM Message RX Channel |
|
IPM Message TX Channel |
|
Driver for Nordic nRF messaging unit, based on nRF IPC peripheral HW. |
|
Include Keyboard scan drivers in system config. |
|
Enable driver for multiple Focaltech capacitive touch panel controllers. This driver should support FT5x06, FT5606, FT5x16, FT6x06, Ft6x36, FT5x06i, FT5336, FT3316, FT5436i, FT5336i and FT5x46. |
|
Enable interrupt support (requires GPIO). |
|
Keyboard scan device driver initialization priority. |
|
Enable driver for the SDL mouse event filter. |
|
Enable the Gecko leuart driver. |
|
Enable SPI 4wire mode (separated MISO and MOSI lines) |
|
Enable backend in native_posix |
|
Set SWO output frequency. Value 0 will select maximum frequency supported by the given MCU. Not all debug probes support high frequency SWO operation. In this case the frequency has to be set manually. SWO value defined by this option will be configured at boot. Most SWO viewer programs will configure SWO frequency when attached to the debug probe. Such configuration will persist only until the device reset. To ensure flawless operation the frequency configured here and by the SWO viewer program has to match. |
|
Number of bytes dedicated for the logger internal buffer. |
|
Enable driver for sharp memory display series LS0XXX7DXXX |
|
Enable/disable internal sensorhub |
|
Number of bits per pixel. |
|
Swap the 2 bytes of a RGB565 pixel. |
|
Name of the display device to use for rendering. |
|
Dots per inch (DPI) |
|
Horizontal screen resolution in pixels |
|
Enable keyboard scan pointer input |
|
Name of the keyboard scan device to use for pointer input. |
|
Invert keyboard scan X axis. This option can be used to align keyboard scan coordinates with the display. |
|
Invert keyboard scan Y axis. This option can be used to align keyboard scan coordinates with the display. |
|
Swap keyboard scan X,Y axes. This option can be used to align keyboard scan coordinates with the display. |
|
Size of the buffer used for rendering screen content as a percentage of total display size. |
|
Vertical screen resolution in pixels |
|
The maximum number of interrupt inputs to any aggregator in the system. |
|
Selects the amount to divide down the fast internal reference clock. The resulting frequency must be in the range 31.25 kHz to 4 MHz. |
|
Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. |
|
Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must be in the range of 2 MHz to 4 MHz. |
|
Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits establish the multiplication factor (M) applied to the reference clock frequency. |
|
If this option is set, the driver does not perform a hardware reset and the CLK_OUT frequency is not set, instead these settings are performed during the initialization of the SoC. |
|
Enable config options for modem drivers. |
|
Choose this setting to enable Sierra Wireless HL7800 LTE-M/NB-IoT modem driver. |
|
Activate shell module that provides modem utilities like sending a command to the modem UART. |
|
Choose this setting to enable u-blox SARA-R4 LTE-CatM1/NB-IoT modem driver. |
|
Choose this setting to use a modem GPIO pin as network indication. |
|
Choose this setting to enable Wistron WNC-M14A2A LTE-M modem driver. NOTE: Currently the pin settings only work with FRDM K64F shield. |
|
Number of multiprocessing-capable cores available to the multicpu API and SMP features. |
|
Use the host terminal (where the native_posix binary was launched) for the Zephyr console |
|
When selected the execution of the process will be slowed down to real time. (if there is a lot of load it may be slower than real time) If deselected, the process will run as fast as possible. Note that this only decouples simulated time from real/wall time. In either case the zephyr kernel and application cannot tell the difference unless they interact with some other driver/device which runs at real time. |
|
The device name to get bindings from in the sample application. |
|
The network application needs IPv6 support to function properly. This option makes sure the network application is initialized properly in order to use IPv6. |
|
Enable IPv6 support. This should be selected by default as there is limited set of network bearers provided that support IPv4. |
|
Enable Bluetooth driver that send and receives IPv6 packets, does header compression on it and writes it to the Bluetooth stack via L2CAP channel. |
|
This workaround is necessary to interoperate with Linux up to 4.10 but it might not be compliant with RFC 7668 as it cause the stack to skip Neighbor Discovery cache causing the destination link address to be omitted. For more details why this is needed see: https://github.com/zephyrproject-rtos/zephyr/issues/3111 |
|
Add support for Ethernet, enabling selecting relevant hardware drivers. If NET_SLIP_TAP is selected, NET_L2_ETHERNET will enable to fully simulate Ethernet through SLIP. |
|
Enable SPIM driver |
|
Enable TWIM driver |
|
This module implements a kernel device driver for the nRF Real Time Counter NRF_RTC1 and provides the standard “system clock driver” interfaces. |
|
This module implements a kernel device driver for the nRF Timer Counter NRF_TIMER0 and provides the standard “system clock driver” interfaces. |
|
The number of level 2 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 2 interrupts. |
|
The number of level 3 interrupt aggregators to support. Each aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 3 interrupts. |
|
Interrupts available will be 0 to NUM_IRQS-1. The minimum value is 17 as the first 16 entries in the vector table are for CPU exceptions. The BSP must provide a valid default. This drives the size of the vector table. |
|
Set the external oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
If the toolchain supports it, this option will pass –print-memory-region to the linker when it is doing it’s first linker pass. Note that the memory regions are symbolic concepts defined by the linker scripts and do not necessarily map directly to the real physical address space. Take also note that some platforms do two passes of the linker so the results do not match exactly to the final elf file. See also rom_report, ram_report and https://sourceware.org/binutils/docs/ld/MEMORY.html |
|
Enable driver for ARM V2M Beetle Pin multiplexer. |
|
Enable driver for Intel S1000 I/O multiplexer. |
|
Enable Port 0. |
|
Enable Port 1. |
|
Just the driver init priority |
|
Enable PS2 0. |
|
Enable PS2 1. |
|
Enable the PWM driver for the SiFive Freedom platform |
|
Enable QEMU virtual instruction counter. The virtual cpu will execute one instruction every 2^N ns of virtual time. This will give deterministic execution times from the guest point of view. |
|
The virtual CPU will execute one instruction every 2^N nanoseconds of virtual time, where N is the value provided here. |
|
This sets the size of the shared memory when using ivshmem-plain device in Qemu. Note that it’s in mega-bytes, so 1 means 1M for Qemu etc.. |
|
Mark all QEMU targets with this variable for checking whether we are running in an emulated environment. |
|
By default BL2 header size in TF-M is 0x400. ROM_START_OFFSET needs to be updated if TF-M switches to use a different header size for BL2. |
|
This option must be selected when separate IPMs are used for TX and RX communication |
|
This option specifies the IPM device name to be used for RX communication |
|
This option specifies the IPM device name to be used for TX communication |
|
Enable support for INTMUX channel 2. |
|
Enable support for INTMUX channel 3. |
|
Enable SDL based emulated display compliant with display driver API. |
|
Enable options for serial drivers. |
|
Interrupt driven |
|
Enables the Nios-II QSPI flash driver. |
|
Specify the device name for the QSPI flash driver. |
|
Any NRF52 simulated SOC with BabbleSim, based on the POSIX arch |
|
Any NRF simulated SOC with BabbleSim, based on the POSIX arch |
|
Use CASA atomic instructions. Defined by SPARC V9 and available in some LEON processors. |
|
Enable support for the SPI hardware bus. |
|
Enable SPI controller port 0. |
|
This sets the supported operation modes at runtime, by the SPI port 0, where: 1 is MASTER mode only (default) 2 is SLAVE mode only 3 is both modes are available. |
|
Enable SPI controller port 1. |
|
Enable SPI controller port 2. |
|
Enable nRF SPI Master with EasyDMA on port 2. |
|
Enable SPI controller port 3. |
|
Enable SPI controller port 5. |
|
Enable SPI controller port 8. |
|
Enable support for Designware’s SPI controllers. |
|
In some case, e.g. ARC HS Development kit, the peripheral space of DesignWare SPI only allows word access, byte access will raise exception. |
|
SPI IP block registers are part of user extended auxiliary registers and thus their access is different than memory mapped registers. |
|
Corresponds to the SSI_TX_FIFO_DEPTH and SSI_RX_FIFO_DEPTH of the DesignWare Synchronous Serial Interface. Depth ranges from 2-256. |
|
SPI NOR Flash |
|
Enable support for nrfx SPI drivers for nRF MCU series. |
|
Enable the SPI peripherals on SiFive Freedom processors |
|
Enable Interrupt support for the SPI Driver of STM32 family. |
|
Enable support for the Microchip XEC QMSPI driver. |
|
Enable Xilinx AXI Quad SPI v3.2 driver. |
|
The SRAM size in kB. The default value comes from /chosen/zephyr,sram in devicetree. The user should generally avoid changing it via menuconfig or in configuration files. |
|
Enable driver for SSD1306 display driver. |
|
Enable driver for SSD16XX compatible controller. |
|
Enable driver for ST7789V display driver. |
|
Enable Dual Core |
|
Set the board system oscillator settling time in us. This should be set by the board’s defconfig. |
|
This option specifies hardware clock. |
|
This option specifies the nominal frequency of the system clock in Hz. For asynchronous timekeeping, the kernel defines a “ticks” concept. A “tick” is the internal count in which the kernel does all its internal uptime and timeout bookeeping. Interrupts are expected to be delivered on tick boundaries to the extent practical, and no fractional ticks are tracked. The choice of tick rate is configurable by this option. Also the number of cycles per tick should be chosen so that 1 millisecond is exactly represented by an integral number of ticks. Defaults on most hardware platforms (ones that support setting arbitrary interrupt timeouts) are expected to be in the range of 10 kHz, with software emulation platforms and legacy drivers using a more traditional 100 Hz value. Note that when available and enabled, in “tickless” mode this config variable specifies the minimum available timing granularity, not necessarily the number or frequency of interrupts delivered to the kernel. A value of 0 completely disables timer support in the kernel. |
|
Enable the Microchip XEC tachometer sensor. |
|
Enable driver for NXP Kinetis temperature sensor. |
|
Manually set the required TFM isolation level. Possible values are 1,2 or 3; the default is set by build configuration. |
|
Build profile used to build tfm_s image. The available values are profile_medium and profile_small. The default profile does not need to have this configuration set. |
|
The dualtimer (DTMR) present in the platform is used as a timer. This option enables the support for the timer. |
|
The timers (TMR) present in the platform are used as timers. This option enables the support for the timers. |
|
This option enables the UART driver for ARM CMSDK APB UART. |
|
Enable this option to use one UART for console. Make sure CONFIG_UART_CONSOLE_ON_DEV_NAME is also set correctly. |
|
This option specifies the name of UART device to be used for UART console. |
|
Enable the Gecko uart driver. |
|
This option enables interrupt support for UART allowing console input and other UART based drivers. |
|
This enables the API for apps to control the serial line, such as baud rate, CTS and RTS. Implementation is up to individual driver. Says no if not sure. |
|
This enables a UART driver for the POSIX ARCH with up to 2 UARTs. For the first UART port, the driver can be configured to either connect to the terminal from which native_posix was run, or into one dedicated pseudoterminal for that UART. |
|
Enable support for nrfx UART drivers for nRF MCU series. Peripherals with the same instance ID cannot be used together, e.g. UART_0 and UARTE_0. |
|
This option enables the NS16550 serial driver. This driver can be used for the serial hardware available on x86 boards. |
|
This option enables the UART driver for the PL011 |
|
Build the driver to utilize UART controller Port 0. |
|
Build the driver to utilize UART controller Port 1. |
|
Enable support for UART_5 on port 5 in the driver. |
|
Enable support for UART_6 on port 12 in the driver. |
|
Enable the RV32M1 LPUART driver. |
|
This option specifies the name of UART device to be used for the SHELL UART backend. In case when DTS is enabled (HAS_DTS), the default value is set from DTS chosen node ‘zephyr,shell-uart’ but can be overridden here. |
|
This option enables the UART driver for Xilinx UART Lite IP. |
|
This option enables the USARTx driver for Atmel SAM MCUs. |
|
Enable USB drivers. |
|
Enable USB support on the STM32 F0, F1, F2, F3, F4, F7, L0, L4 and G4 family of processors. |
|
USB device Manufacturer string. MUST be configured by vendor. |
|
Ethernet Control Model (ECM) is a part of Communications Device Class (CDC) USB protocol specified by USB-IF. |
|
Ethernet Emulation Model (EEM) is part of Communications Device Class (CDC) USB protocol and can be used to encapsulate Ethernet frames for transport over USB. |
|
USB device product ID. MUST be configured by vendor. |
|
USB device Product string. MUST be configured by vendor. |
|
Enable USB device stack. |
|
USB device vendor ID. MUST be configured by vendor. |
|
Designware USB Device Controller Driver. |
|
Indicates whether or not USB specification version 2.0 is supported |
|
Native Posix USB Device Controller Driver. |
|
nRF USB Device Controller Driver |
|
Set buffer size for Standard, Class and Vendor request handlers |
|
Enable this option to use the USB UART for console output. The output can be viewed from the USB host via /dev/ttyACM* port. Note that console inputs from the USB UART are not functional yet. Also since the USB layer currently doesn’t support multiple interfaces, this shouldn’t be selected in conjunction with, say, USB Mass Storage. |
|
When enabled, the application will be linked into the flash partition selected by the zephyr,code-partition property in /chosen in devicetree. When this is disabled, the flash load offset and size can be set manually below. |
|
Enable CMSDK APB Watchdog (WDOG_CMSDK_APB) Driver for ARM family of MCUs. |
|
Wi-Fi Drivers |
|
Espressif ESP8266 and ESP32 support |
|
Inventek eS-WiFi support |
|
WINC1500 driver support |
|
Set the external oscillator frequency in Hz. This should be set by the board’s defconfig. |
|
Test function thread stack size |