CONFIG_2ND_LVL_INTR_00_OFFSET¶

Level 1 IRQ line for 2ND level aggregator 0

Type: int

Help¶

This is the level $(prev-level-num) interrupt number for level
$(cur-level-num) interrupt aggregator $(aggregator).

Direct dependencies¶

(Includes any dependencies from ifs and menus.)

Defaults¶

Kconfig definitions¶

At <Zephyr Boards>/xtensa/intel_adsp_cavs15/Kconfig.defconfig:19

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default CAVS_ICTL_0_OFFSET
    depends on BOARD_INTEL_ADSP_CAVS15

At <Zephyr Boards>/xtensa/intel_adsp_cavs18/Kconfig.defconfig:19

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default CAVS_ICTL_0_OFFSET
    depends on BOARD_INTEL_ADSP_CAVS18

At <Zephyr Boards>/xtensa/intel_adsp_cavs20/Kconfig.defconfig:19

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default CAVS_ICTL_0_OFFSET
    depends on BOARD_INTEL_ADSP_CAVS20

At <Zephyr Boards>/xtensa/intel_adsp_cavs25/Kconfig.defconfig:19

Included via Kconfig:8 → Kconfig.zephyr:22

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default CAVS_ICTL_0_OFFSET
    depends on BOARD_INTEL_ADSP_CAVS25

At <Zephyr Boards>/xtensa/intel_s1000_crb/Kconfig.defconfig:21

Included via Kconfig:8 → Kconfig.zephyr:22

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config 2ND_LVL_INTR_00_OFFSET
    int
    default CAVS_ICTL_0_OFFSET
    depends on BOARD_INTEL_S1000_CRB

At <Zephyr SoC>/riscv/openisa_rv32m1/Kconfig.defconfig:65

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 24
    depends on MULTI_LEVEL_INTERRUPTS && SOC_OPENISA_RV32M1_RISCV32

At <Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:39

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_RISCV_ANDES_V5

At <Zephyr SoC>/riscv/riscv-privilege/miv/Kconfig.defconfig.series:26

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_RISCV32_MIV

At <Zephyr SoC>/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:26

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM

At <Zephyr SoC>/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:27

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_STARFIVE_JH71XX

At <Zephyr SoC>/riscv/riscv-privilege/virt/Kconfig.defconfig.series:27

Included via Kconfig:8 → Kconfig.zephyr:25 → <BuildDir>/kconfig/Kconfig.soc.defconfig:1 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_RISCV_VIRT

At <Zephyr SoC>/riscv/openisa_rv32m1/Kconfig.defconfig:65

Included via Kconfig:8 → Kconfig.zephyr:27

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 24
    depends on MULTI_LEVEL_INTERRUPTS && SOC_OPENISA_RV32M1_RISCV32

At <Zephyr SoC>/riscv/riscv-privilege/andes_v5/Kconfig.defconfig.series:39

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_RISCV_ANDES_V5

At <Zephyr SoC>/riscv/riscv-privilege/miv/Kconfig.defconfig.series:26

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_RISCV32_MIV

At <Zephyr SoC>/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series:26

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_RISCV_SIFIVE_FREEDOM

At <Zephyr SoC>/riscv/riscv-privilege/starfive_jh71xx/Kconfig.defconfig.series:27

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_STARFIVE_JH71XX

At <Zephyr SoC>/riscv/riscv-privilege/virt/Kconfig.defconfig.series:27

Included via Kconfig:8 → Kconfig.zephyr:27 → <Zephyr SoC>/riscv/riscv-privilege/Kconfig.defconfig:6

Menu path: (Top)

config 2ND_LVL_INTR_00_OFFSET
    int
    default 11
    depends on SOC_SERIES_RISCV_VIRT

At <Zephyr Driver>/interrupt_controller/Kconfig.multilevel.aggregator_template:3

Included via Kconfig:8 → Kconfig.zephyr:42 → <Zephyr Driver>/Kconfig:28 → <Zephyr Driver>/interrupt_controller/Kconfig:48 → <Zephyr Driver>/interrupt_controller/Kconfig.multilevel:59

Menu path: (Top) → Device Drivers → Interrupt Controllers → Multi-level interrupt support → Second-level interrupt support

config 2ND_LVL_INTR_00_OFFSET
    int "Level 1 IRQ line for 2ND level aggregator 0"
    default 0
    depends on 2ND_LEVEL_INTERRUPTS
    help
      This is the level $(prev-level-num) interrupt number for level
      $(cur-level-num) interrupt aggregator $(aggregator).

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)