CONFIG_CLOCK_STM32_PLL3_Q_DIVISOR

PLL3 Q Divisor

Type: int

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PLL3 Q Output divisor, allowed values: 1-128.

Direct dependencies

CLOCK_STM32_PLL3_Q_ENABLE && CLOCK_STM32_PLL3_ENABLE && SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL

(Includes any dependencies from ifs and menus.)

Default

• 2

Kconfig definition

At <Zephyr Driver>/clock_control/Kconfig.stm32h7:148

Included via Kconfig:8 → Kconfig.zephyr:42 → <Zephyr Driver>/Kconfig:56 → <Zephyr Driver>/clock_control/Kconfig:25 → <Zephyr Driver>/clock_control/Kconfig.stm32:153

Menu path: (Top) → Device Drivers → Hardware clock controller support → STM32 Reset & Clock Control → Enable PLL3 → Enable PLL3 Q output

config CLOCK_STM32_PLL3_Q_DIVISOR
    int "PLL3 Q Divisor"
    range 1 128
    default 2
    depends on CLOCK_STM32_PLL3_Q_ENABLE && CLOCK_STM32_PLL3_ENABLE && SOC_SERIES_STM32H7X && !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X && CLOCK_CONTROL_STM32_CUBE && CLOCK_CONTROL
    help
      PLL3 Q Output divisor, allowed values: 1-128.

(The ‘depends on’ condition includes propagated dependencies from ifs and menus.)