| Zephyr Project API 4.2.99
    A Scalable Open Source RTOS | 
Go to the source code of this file.
| Macros | |
| #define | MIPI_DBI_MODE_SPI_3WIRE 0x1 | 
| SPI 3 wire (Type C1). | |
| #define | MIPI_DBI_MODE_SPI_4WIRE 0x2 | 
| SPI 4 wire (Type C3). | |
| #define | MIPI_DBI_TE_NO_EDGE 0x0 | 
| MIPI DBI tearing enable synchronization is disabled. | |
| #define | MIPI_DBI_TE_RISING_EDGE 0x1 | 
| MIPI DBI tearing enable synchronization on rising edge of TE signal. | |
| #define | MIPI_DBI_TE_FALLING_EDGE 0x2 | 
| MIPI DBI tearing enable synchronization on falling edge of TE signal. | |
| #define | MIPI_DBI_SPI_XFR_8BIT 8 | 
| SPI transfer of DBI commands as 8-bit blocks, the default behaviour in SPI 4 wire (Type C3) mode. | |
| #define | MIPI_DBI_SPI_XFR_16BIT 16 | 
| SPI transfer of DBI commands as 16-bit blocks, a rare and seldom behaviour in SPI 4 wire (Type C3) mode. | |
| Parallel Bus protocol for MIPI DBI Type A based on Motorola 6800 bus. | |
|          -.   .--------.      .------------------------
CS        '---'        '---'
         -------------------------------------------
RESX
              .--------------------------------
D/CX     ----------'
R/WX     -------------------------------------------
         -------------------------------------------
E
          .--------.   .--------------------------.
D[15:0]/ -| COMMAND|---|  DATA                    |
D[8:0]/   '--------'   '--------------------------'
D[7:0]
Please refer to the MIPI DBI specification for a detailed cycle diagram. | |
| #define | MIPI_DBI_MODE_6800_BUS_16_BIT 0x3 | 
| Motorola 6800 parallel bus, 16-bit width. | |
| #define | MIPI_DBI_MODE_6800_BUS_9_BIT 0x4 | 
| Motorola 6800 parallel bus, 9-bit width. | |
| #define | MIPI_DBI_MODE_6800_BUS_8_BIT 0x5 | 
| Motorola 6800 parallel bus, 8-bit width. | |
| Parallel Bus protocol for MIPI DBI Type B based on Intel 8080 bus. | |
|          -.                                  .-
CS        '---------------------------------------'
         -------------------------------------------
RESX
         --.              .----------------------------
D/CX       '-----------'
         ---.   .--------.   .----------------------
WRX         '---'   '---'
         -------------------------------------------
RDX
            .--------.   .--------------------------.
D[15:0]/ ---| COMMAND|---|  DATA                    |
D[8:0]/     '--------'   '--------------------------'
D[7:0]
Please refer to the MIPI DBI specification for a detailed cycle diagram. | |
| #define | MIPI_DBI_MODE_8080_BUS_16_BIT 0x6 | 
| Intel 8080 parallel bus, 16-bit width. | |
| #define | MIPI_DBI_MODE_8080_BUS_9_BIT 0x7 | 
| Intel 8080 parallel bus, 9-bit width. | |
| #define | MIPI_DBI_MODE_8080_BUS_8_BIT 0x8 | 
| Intel 8080 parallel bus, 8-bit width. | |
| Color coding for MIPI DBI Type A or Type B interface. | |
| #define | MIPI_DBI_MODE_RGB332 (0x1 << 4U) | 
| RGB332 (8 bpp). | |
| #define | MIPI_DBI_MODE_RGB444 (0x2 << 4U) | 
| RGB444 (12 bpp). | |
| #define | MIPI_DBI_MODE_RGB565 (0x3 << 4U) | 
| RGB565 (16 bpp). | |
| #define | MIPI_DBI_MODE_RGB666_1 (0x4 << 4U) | 
| RGB666 (18 bpp). | |
| #define | MIPI_DBI_MODE_RGB666_2 (0x5 << 4U) | 
| RGB666 (18 bpp). | |
| #define | MIPI_DBI_MODE_RGB888_1 (0x6 << 4U) | 
| RGB666 (18 bpp). | |
| #define | MIPI_DBI_MODE_RGB888_2 (0x7 << 4U) | 
| RGB888 (24 bpp). | |