renesas_ra_cgc.h File Reference

#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/ra_clock.h>

Go to the source code of this file.

Data Structures
struct	clock_control_ra_pclk_cfg
struct	clock_control_ra_subsys_cfg

Macros
#define	RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value)    COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value))
#define	RA_CGC_CLK_SRC(node_id)
#define	RA_CGC_CLK_DIV(clk, prop, default_value)
#define	RA_CGC_DIV_BCLK(n)   UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
#define	RA_CGC_DIV_CANFDCLK(n)   UTIL_CAT(BSP_CLOCKS_CANFD_CLOCK_DIV_, n)
#define	RA_CGC_DIV_CECCLK(n)   UTIL_CAT(BSP_CLOCKS_CEC_CLOCK_DIV_, n)
#define	RA_CGC_DIV_CLKOUT(n)   UTIL_CAT(BSP_CLOCKS_CLKOUT_DIV_, n)
#define	RA_CGC_DIV_CPUCLK(n)   UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
#define	RA_CGC_DIV_FCLK(n)   UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
#define	RA_CGC_DIV_I3CCLK(n)   UTIL_CAT(BSP_CLOCKS_I3C_CLOCK_DIV_, n)
#define	RA_CGC_DIV_ICLK(n)   UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
#define	RA_CGC_DIV_LCDCLK(n)   UTIL_CAT(BSP_CLOCKS_LCD_CLOCK_DIV_, n)
#define	RA_CGC_DIV_OCTASPICLK(n)   UTIL_CAT(BSP_CLOCKS_OCTA_CLOCK_DIV_, n)
#define	RA_CGC_DIV_PCLKA(n)   UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
#define	RA_CGC_DIV_PCLKB(n)   UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
#define	RA_CGC_DIV_PCLKC(n)   UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
#define	RA_CGC_DIV_PCLKD(n)   UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
#define	RA_CGC_DIV_PCLKE(n)   UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)
#define	RA_CGC_DIV_PLL(n)   UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
#define	RA_CGC_DIV_PLLP(n)   UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
#define	RA_CGC_DIV_PLLQ(n)   UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
#define	RA_CGC_DIV_PLLR(n)   UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
#define	RA_CGC_DIV_PLL2(n)   UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
#define	RA_CGC_DIV_PLL2P(n)   UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
#define	RA_CGC_DIV_PLL2Q(n)   UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
#define	RA_CGC_DIV_PLL2R(n)   UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)
#define	RA_CGC_DIV_SCICLK(n)   UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n)
#define	RA_CGC_DIV_SPICLK(n)   UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n)
#define	RA_CGC_DIV_U60CLK(n)   UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n)
#define	RA_CGC_DIV_UCLK(n)   UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n)
#define	BSP_CLOCKS_SOURCE_PLL   BSP_CLOCKS_SOURCE_CLOCK_PLL
#define	BSP_CLOCKS_SOURCE_PLLP   BSP_CLOCKS_SOURCE_CLOCK_PLL
#define	BSP_CLOCKS_SOURCE_PLLQ   BSP_CLOCKS_SOURCE_CLOCK_PLL1Q
#define	BSP_CLOCKS_SOURCE_PLLR   BSP_CLOCKS_SOURCE_CLOCK_PLL1R
#define	BSP_CLOCKS_SOURCE_PLL2   BSP_CLOCKS_SOURCE_CLOCK_PLL2
#define	BSP_CLOCKS_SOURCE_PLL2P   BSP_CLOCKS_SOURCE_CLOCK_PLL2
#define	BSP_CLOCKS_SOURCE_PLL2Q   BSP_CLOCKS_SOURCE_CLOCK_PLL2Q
#define	BSP_CLOCKS_SOURCE_PLL2R   BSP_CLOCKS_SOURCE_CLOCK_PLL2R
#define	BSP_CLOCKS_CLKOUT_DIV_1   (0)
#define	BSP_CLOCKS_CLKOUT_DIV_2   (1)
#define	BSP_CLOCKS_CLKOUT_DIV_4   (2)
#define	BSP_CLOCKS_CLKOUT_DIV_8   (3)
#define	BSP_CLOCKS_CLKOUT_DIV_16   (4)
#define	BSP_CLOCKS_CLKOUT_DIV_32   (5)
#define	BSP_CLOCKS_CLKOUT_DIV_64   (6)
#define	BSP_CLOCKS_CLKOUT_DIV_128   (7)

Macro Definition Documentation

BSP_CLOCKS_CLKOUT_DIV_1

#define BSP_CLOCKS_CLKOUT_DIV_1   (0)

BSP_CLOCKS_CLKOUT_DIV_128

#define BSP_CLOCKS_CLKOUT_DIV_128   (7)

BSP_CLOCKS_CLKOUT_DIV_16

#define BSP_CLOCKS_CLKOUT_DIV_16   (4)

BSP_CLOCKS_CLKOUT_DIV_2

#define BSP_CLOCKS_CLKOUT_DIV_2   (1)

BSP_CLOCKS_CLKOUT_DIV_32

#define BSP_CLOCKS_CLKOUT_DIV_32   (5)

BSP_CLOCKS_CLKOUT_DIV_4

#define BSP_CLOCKS_CLKOUT_DIV_4   (2)

BSP_CLOCKS_CLKOUT_DIV_64

#define BSP_CLOCKS_CLKOUT_DIV_64   (6)

BSP_CLOCKS_CLKOUT_DIV_8

#define BSP_CLOCKS_CLKOUT_DIV_8   (3)

BSP_CLOCKS_SOURCE_PLL

#define BSP_CLOCKS_SOURCE_PLL   BSP_CLOCKS_SOURCE_CLOCK_PLL

BSP_CLOCKS_SOURCE_PLL2

#define BSP_CLOCKS_SOURCE_PLL2   BSP_CLOCKS_SOURCE_CLOCK_PLL2

BSP_CLOCKS_SOURCE_PLL2P

#define BSP_CLOCKS_SOURCE_PLL2P   BSP_CLOCKS_SOURCE_CLOCK_PLL2

BSP_CLOCKS_SOURCE_PLL2Q

#define BSP_CLOCKS_SOURCE_PLL2Q   BSP_CLOCKS_SOURCE_CLOCK_PLL2Q

BSP_CLOCKS_SOURCE_PLL2R

#define BSP_CLOCKS_SOURCE_PLL2R   BSP_CLOCKS_SOURCE_CLOCK_PLL2R

BSP_CLOCKS_SOURCE_PLLP

#define BSP_CLOCKS_SOURCE_PLLP   BSP_CLOCKS_SOURCE_CLOCK_PLL

BSP_CLOCKS_SOURCE_PLLQ

#define BSP_CLOCKS_SOURCE_PLLQ   BSP_CLOCKS_SOURCE_CLOCK_PLL1Q

BSP_CLOCKS_SOURCE_PLLR

#define BSP_CLOCKS_SOURCE_PLLR   BSP_CLOCKS_SOURCE_CLOCK_PLL1R

RA_CGC_CLK_DIV

#define RA_CGC_CLK_DIV	(		clk,
			prop,
			default_value
	)

Value:

        UTIL_CAT(RA_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk))                                  \
        (RA_CGC_PROP_HAS_STATUS_OKAY_OR(clk, prop, default_value))

RA_CGC_CLK_SRC

#define RA_CGC_CLK_SRC

(

node_id

)

Value:

        COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay),                                             \
                    (UTIL_CAT(BSP_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))),        \
                    (BSP_CLOCKS_CLOCK_DISABLED))

RA_CGC_DIV_BCLK

#define RA_CGC_DIV_BCLK

(

n

)

UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

RA_CGC_DIV_CANFDCLK

#define RA_CGC_DIV_CANFDCLK

(

n

)

UTIL_CAT(BSP_CLOCKS_CANFD_CLOCK_DIV_, n)

RA_CGC_DIV_CECCLK

#define RA_CGC_DIV_CECCLK

(

n

)

UTIL_CAT(BSP_CLOCKS_CEC_CLOCK_DIV_, n)

RA_CGC_DIV_CLKOUT

#define RA_CGC_DIV_CLKOUT

(

n

)

UTIL_CAT(BSP_CLOCKS_CLKOUT_DIV_, n)

RA_CGC_DIV_CPUCLK

#define RA_CGC_DIV_CPUCLK

(

n

)

UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

RA_CGC_DIV_FCLK

#define RA_CGC_DIV_FCLK

(

n

)

UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

RA_CGC_DIV_I3CCLK

#define RA_CGC_DIV_I3CCLK

(

n

)

UTIL_CAT(BSP_CLOCKS_I3C_CLOCK_DIV_, n)

RA_CGC_DIV_ICLK

#define RA_CGC_DIV_ICLK

(

n

)

UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

RA_CGC_DIV_LCDCLK

#define RA_CGC_DIV_LCDCLK

(

n

)

UTIL_CAT(BSP_CLOCKS_LCD_CLOCK_DIV_, n)

RA_CGC_DIV_OCTASPICLK

#define RA_CGC_DIV_OCTASPICLK

(

n

)

UTIL_CAT(BSP_CLOCKS_OCTA_CLOCK_DIV_, n)

RA_CGC_DIV_PCLKA

#define RA_CGC_DIV_PCLKA

(

n

)

UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

RA_CGC_DIV_PCLKB

#define RA_CGC_DIV_PCLKB

(

n

)

UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

RA_CGC_DIV_PCLKC

#define RA_CGC_DIV_PCLKC

(

n

)

UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

RA_CGC_DIV_PCLKD

#define RA_CGC_DIV_PCLKD

(

n

)

UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

RA_CGC_DIV_PCLKE

#define RA_CGC_DIV_PCLKE

(

n

)

UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n)

RA_CGC_DIV_PLL

#define RA_CGC_DIV_PLL

(

n

)

UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

RA_CGC_DIV_PLL2

#define RA_CGC_DIV_PLL2

(

n

)

UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

RA_CGC_DIV_PLL2P

#define RA_CGC_DIV_PLL2P

(

n

)

UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

RA_CGC_DIV_PLL2Q

#define RA_CGC_DIV_PLL2Q

(

n

)

UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

RA_CGC_DIV_PLL2R

#define RA_CGC_DIV_PLL2R

(

n

)

UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

RA_CGC_DIV_PLLP

#define RA_CGC_DIV_PLLP

(

n

)

UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

RA_CGC_DIV_PLLQ

#define RA_CGC_DIV_PLLQ

(

n

)

UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

RA_CGC_DIV_PLLR

#define RA_CGC_DIV_PLLR

(

n

)

UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n)

RA_CGC_DIV_SCICLK

#define RA_CGC_DIV_SCICLK

(

n

)

UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n)

RA_CGC_DIV_SPICLK

#define RA_CGC_DIV_SPICLK

(

n

)

UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n)

RA_CGC_DIV_U60CLK

#define RA_CGC_DIV_U60CLK

(

n

)

UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n)

RA_CGC_DIV_UCLK

#define RA_CGC_DIV_UCLK

(

n

)

UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n)

RA_CGC_PROP_HAS_STATUS_OKAY_OR

#define RA_CGC_PROP_HAS_STATUS_OKAY_OR	(		node_id,
			prop,
			default_value
	)		COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value))