Zephyr Project API 3.7.0
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
stm32f7_clock.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2022 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_
8
10
14#define STM32_CLOCK_BUS_AHB1 0x030
15#define STM32_CLOCK_BUS_AHB2 0x034
16#define STM32_CLOCK_BUS_AHB3 0x038
17#define STM32_CLOCK_BUS_APB1 0x040
18#define STM32_CLOCK_BUS_APB2 0x044
19#define STM32_CLOCK_BUS_APB3 0x0A8
20
21#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
22#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
23
25/* RM0386, 0390, 0402, 0430 ยง Dedicated Clock configuration register (RCC_DCKCFGRx) */
26
28/* defined in stm32_common_clocks.h */
29
31/* Low speed clocks defined in stm32_common_clocks.h */
32#define STM32_SRC_HSI (STM32_SRC_LSI + 1)
34#define STM32_SRC_PLL_P (STM32_SRC_HSI + 1)
35#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)
36#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)
38#define STM32_SRC_PCLK (STM32_SRC_PLL_R + 1)
39
40
41#define STM32_CLOCK_REG_MASK 0xFFU
42#define STM32_CLOCK_REG_SHIFT 0U
43#define STM32_CLOCK_SHIFT_MASK 0x1FU
44#define STM32_CLOCK_SHIFT_SHIFT 8U
45#define STM32_CLOCK_MASK_MASK 0x7U
46#define STM32_CLOCK_MASK_SHIFT 13U
47#define STM32_CLOCK_VAL_MASK 0x7U
48#define STM32_CLOCK_VAL_SHIFT 16U
49
63#define STM32_CLOCK(val, mask, shift, reg) \
64 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
65 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
66 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
67 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
68
70#define CFGR_REG 0x08
71
73#define BDCR_REG 0x70
74
77#define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG)
79#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG)
80
82#define DCKCFGR1_REG 0x8C
83#define DCKCFGR2_REG 0x90
84
87#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, DCKCFGR2_REG)
88#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, DCKCFGR2_REG)
89#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, DCKCFGR2_REG)
90#define USART4_SEL(val) STM32_CLOCK(val, 3, 6, DCKCFGR2_REG)
91#define USART5_SEL(val) STM32_CLOCK(val, 3, 8, DCKCFGR2_REG)
92#define USART6_SEL(val) STM32_CLOCK(val, 3, 10, DCKCFGR2_REG)
93#define USART7_SEL(val) STM32_CLOCK(val, 3, 12, DCKCFGR2_REG)
94#define USART8_SEL(val) STM32_CLOCK(val, 3, 14, DCKCFGR2_REG)
95#define I2C1_SEL(val) STM32_CLOCK(val, 3, 16, DCKCFGR2_REG)
96#define I2C2_SEL(val) STM32_CLOCK(val, 3, 18, DCKCFGR2_REG)
97#define I2C3_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR2_REG)
98#define I2C4_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG)
99#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 24, DCKCFGR2_REG)
100#define CEC_SEL(val) STM32_CLOCK(val, 1, 26, DCKCFGR2_REG)
101#define CK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR2_REG)
102#define SDMMC1_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR2_REG)
103#define SDMMC2_SEL(val) STM32_CLOCK(val, 1, 29, DCKCFGR2_REG)
104#define DSI_SEL(val) STM32_CLOCK(val, 1, 30, DCKCFGR2_REG)
105
106#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */