stm32f7_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_CLOCK_BUS_AHB1   0x030
	Domain clocks.
#define	STM32_CLOCK_BUS_AHB2   0x034
#define	STM32_CLOCK_BUS_AHB3   0x038
#define	STM32_CLOCK_BUS_APB1   0x040
#define	STM32_CLOCK_BUS_APB2   0x044
#define	STM32_CLOCK_BUS_APB3   0x0A8
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3
#define	STM32_SRC_HSI   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_HSE   (STM32_SRC_HSI + 1)
#define	STM32_SRC_PLL_P   (STM32_SRC_HSE + 1)
	PLL clock outputs.
#define	STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)
#define	STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)
#define	STM32_SRC_PCLK   (STM32_SRC_PLL_R + 1)
	Peripheral bus clock.
#define	STM32_SRC_PLLI2S_R   (STM32_SRC_PCLK + 1)
#define	STM32_CLOCK_REG_MASK   0xFFU
#define	STM32_CLOCK_REG_SHIFT   0U
#define	STM32_CLOCK_SHIFT_MASK   0x1FU
#define	STM32_CLOCK_SHIFT_SHIFT   8U
#define	STM32_CLOCK_MASK_MASK   0x7U
#define	STM32_CLOCK_MASK_SHIFT   13U
#define	STM32_CLOCK_VAL_MASK   0x7U
#define	STM32_CLOCK_VAL_SHIFT   16U
#define	STM32_DOMAIN_CLOCK(val, mask, shift, reg)
	STM32 clock configuration bit field.
#define	CFGR_REG   0x08
	RCC_CFGRx register offset.
#define	BDCR_REG   0x70
	RCC_BDCR register offset.
#define	I2S_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
	Device domain clocks selection helpers.
#define	MCO1_SEL(val)   STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
#define	MCO1_PRE(val)   STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
#define	MCO2_SEL(val)   STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
#define	MCO2_PRE(val)   STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
#define	MCO_PRE_DIV_1   0
#define	MCO_PRE_DIV_2   4
#define	MCO_PRE_DIV_3   5
#define	MCO_PRE_DIV_4   6
#define	MCO_PRE_DIV_5   7
#define	RTC_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
	BDCR devices.
#define	DCKCFGR1_REG   0x8C
	RCC_DKCFGR register offset.
#define	DCKCFGR2_REG   0x90
#define	USART1_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG)
	Dedicated clocks configuration register selection helpers.
#define	USART2_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG)
#define	USART3_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG)
#define	USART4_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 6, DCKCFGR2_REG)
#define	USART5_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 8, DCKCFGR2_REG)
#define	USART6_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 10, DCKCFGR2_REG)
#define	USART7_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 12, DCKCFGR2_REG)
#define	USART8_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 14, DCKCFGR2_REG)
#define	I2C1_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 16, DCKCFGR2_REG)
#define	I2C2_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 18, DCKCFGR2_REG)
#define	I2C3_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR2_REG)
#define	I2C4_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)
#define	LPTIM1_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 24, DCKCFGR2_REG)
#define	CEC_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 26, DCKCFGR2_REG)
#define	CK48M_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)
#define	SDMMC1_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)
#define	SDMMC2_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR2_REG)
#define	DSI_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 30, DCKCFGR2_REG)

Macro Definition Documentation

BDCR_REG

#define BDCR_REG   0x70

RCC_BDCR register offset.

CEC_SEL

#define CEC_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 26, DCKCFGR2_REG)

CFGR_REG

#define CFGR_REG   0x08

RCC_CFGRx register offset.

CK48M_SEL

#define CK48M_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)

DCKCFGR1_REG

#define DCKCFGR1_REG   0x8C

RCC_DKCFGR register offset.

DCKCFGR2_REG

#define DCKCFGR2_REG   0x90

DSI_SEL

#define DSI_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 30, DCKCFGR2_REG)

I2C1_SEL

#define I2C1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 16, DCKCFGR2_REG)

I2C2_SEL

#define I2C2_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 18, DCKCFGR2_REG)

I2C3_SEL

#define I2C3_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR2_REG)

I2C4_SEL

#define I2C4_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)

I2S_SEL

#define I2S_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)

Device domain clocks selection helpers.

CFGR devices

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 24, DCKCFGR2_REG)

MCO1_PRE

#define MCO1_PRE

(

val

)

STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)

MCO2_PRE

#define MCO2_PRE

(

val

)

STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)

MCO2_SEL

#define MCO2_SEL

(

val

)

STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)

MCO_PRE_DIV_1

#define MCO_PRE_DIV_1   0

MCO_PRE_DIV_2

#define MCO_PRE_DIV_2   4

MCO_PRE_DIV_3

#define MCO_PRE_DIV_3   5

MCO_PRE_DIV_4

#define MCO_PRE_DIV_4   6

MCO_PRE_DIV_5

#define MCO_PRE_DIV_5   7

RTC_SEL

#define RTC_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)

BDCR devices.

SDMMC1_SEL

#define SDMMC1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)

SDMMC2_SEL

#define SDMMC2_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR2_REG)

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x030

Domain clocks.

Bus clocks

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x034

STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x038

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x040

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x044

STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x0A8

STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

STM32_DOMAIN_CLOCK

#define STM32_DOMAIN_CLOCK	(		val,
			mask,
			shift,
			reg
	)

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32 clock configuration bit field.

• reg (1/2/3) [ 0 : 7 ]
• shift (0..31) [ 8 : 12 ]
• mask (0x1, 0x3, 0x7) [ 13 : 15 ]
• val (0..7) [ 16 : 18 ]

Parameters

reg	RCC_CFGRx register offset
shift	Position within RCC_CFGRx.
mask	Mask for the RCC_CFGRx field.
val	Clock value (0, 1, ... 7).

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_HSI + 1)

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_PCLK

#define STM32_SRC_PCLK   (STM32_SRC_PLL_R + 1)

Peripheral bus clock.

STM32_SRC_PLL_P

#define STM32_SRC_PLL_P   (STM32_SRC_HSE + 1)

PLL clock outputs.

STM32_SRC_PLL_Q

#define STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)

STM32_SRC_PLL_R

#define STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)

STM32_SRC_PLLI2S_R

#define STM32_SRC_PLLI2S_R   (STM32_SRC_PCLK + 1)

USART1_SEL

#define USART1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG)

Dedicated clocks configuration register selection helpers.

DKCFGR2 devices

USART2_SEL

#define USART2_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG)

USART3_SEL

#define USART3_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG)

USART4_SEL

#define USART4_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 6, DCKCFGR2_REG)

USART5_SEL

#define USART5_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 8, DCKCFGR2_REG)

USART6_SEL

#define USART6_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 10, DCKCFGR2_REG)

USART7_SEL

#define USART7_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 12, DCKCFGR2_REG)

USART8_SEL

#define USART8_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 14, DCKCFGR2_REG)