Zephyr Project API 4.2.99
A Scalable Open Source RTOS
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stm32h5_clock.h
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1/*
2 * Copyright (c) 2023 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_
8
10
13/* RM0481/0492, Table 47 Kernel clock distribution summary */
14
16/* defined in stm32_common_clocks.h */
18/* Low speed clocks defined in stm32_common_clocks.h */
19#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
20#define STM32_SRC_CSI (STM32_SRC_HSE + 1)
21#define STM32_SRC_HSI (STM32_SRC_CSI + 1)
22#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
24#define STM32_SRC_HCLK (STM32_SRC_HSI48 + 1)
25#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
26#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
27#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
28#define STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK3 + 1)
29#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
31#define STM32_SRC_PLL1_P (STM32_SRC_TIMPCLK2 + 1)
32#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)
33#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)
34#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
35#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
36#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
37#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
38#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
39#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
41#define STM32_SRC_CKPER (STM32_SRC_PLL3_R + 1)
42
43
45#define STM32_CLOCK_BUS_AHB1 0x088
46#define STM32_CLOCK_BUS_AHB2 0x08C
47#define STM32_CLOCK_BUS_AHB4 0x094
48#define STM32_CLOCK_BUS_APB1 0x09c
49#define STM32_CLOCK_BUS_APB1_2 0x0A0
50#define STM32_CLOCK_BUS_APB2 0x0A4
51#define STM32_CLOCK_BUS_APB3 0x0A8
52
53#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
54#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
55
57#define CCIPR1_REG 0xD8
58#define CCIPR2_REG 0xDC
59#define CCIPR3_REG 0xE0
60#define CCIPR4_REG 0xE4
61#define CCIPR5_REG 0xE8
62
64#define BDCR_REG 0xF0
65
67#define CFGR1_REG 0x1C
68
71#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG)
72#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 3, CCIPR1_REG)
73#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR1_REG)
74#define USART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 9, CCIPR1_REG)
75#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR1_REG)
76#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 15, CCIPR1_REG)
77#define USART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 18, CCIPR1_REG)
78#define USART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 21, CCIPR1_REG)
79#define USART9_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR1_REG)
80#define USART10_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 27, CCIPR1_REG)
81#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG)
82
84#define USART11_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR2_REG)
85#define USART12_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR2_REG)
86#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG)
87#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR2_REG)
88#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG)
89#define LPTIM4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR2_REG)
90#define LPTIM5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR2_REG)
91#define LPTIM6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, CCIPR2_REG)
92
94#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR3_REG)
95#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 3, CCIPR3_REG)
96#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR3_REG)
97#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 9, CCIPR3_REG)
98#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG)
99#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 15, CCIPR2_REG)
100#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR3_REG)
101
103#define OCTOSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR4_REG)
104#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR4_REG)
105#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR4_REG)
106#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR4_REG)
107#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 7, CCIPR4_REG)
108#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR4_REG)
109#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR4_REG)
110#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR4_REG)
111#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR4_REG)
112#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR4_REG)
113
115#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR5_REG)
116#define DAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 3, CCIPR5_REG)
117#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR5_REG)
118#define CEC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR5_REG)
119#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR5_REG)
120#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR5_REG)
121#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 19, CCIPR5_REG)
122#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR5_REG)
123
125#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
126
128#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 22, CFGR1_REG)
129#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 18, CFGR1_REG)
130#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 25, CFGR1_REG)
131#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xF, 29, CFGR1_REG)
132
133/* MCO prescaler : division factor */
134#define MCO_PRE_DIV_1 1
135#define MCO_PRE_DIV_2 2
136#define MCO_PRE_DIV_3 3
137#define MCO_PRE_DIV_4 4
138#define MCO_PRE_DIV_5 5
139#define MCO_PRE_DIV_6 6
140#define MCO_PRE_DIV_7 7
141#define MCO_PRE_DIV_8 8
142#define MCO_PRE_DIV_9 9
143#define MCO_PRE_DIV_10 10
144#define MCO_PRE_DIV_11 11
145#define MCO_PRE_DIV_12 12
146#define MCO_PRE_DIV_13 13
147#define MCO_PRE_DIV_14 14
148#define MCO_PRE_DIV_15 15
149
150#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ */