Zephyr Project API 3.7.0
A Scalable Open Source RTOS
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stm32h5_clock.h File Reference

Go to the source code of this file.

Macros

#define STM32_SRC_HSE   (STM32_SRC_LSI + 1)
 Domain clocks.
 
#define STM32_SRC_CSI   (STM32_SRC_HSE + 1)
 
#define STM32_SRC_HSI   (STM32_SRC_CSI + 1)
 
#define STM32_SRC_HSI48   (STM32_SRC_HSI + 1)
 
#define STM32_SRC_PLL1_P   (STM32_SRC_HSI48 + 1)
 PLL outputs.
 
#define STM32_SRC_PLL1_Q   (STM32_SRC_PLL1_P + 1)
 
#define STM32_SRC_PLL1_R   (STM32_SRC_PLL1_Q + 1)
 
#define STM32_SRC_PLL2_P   (STM32_SRC_PLL1_R + 1)
 
#define STM32_SRC_PLL2_Q   (STM32_SRC_PLL2_P + 1)
 
#define STM32_SRC_PLL2_R   (STM32_SRC_PLL2_Q + 1)
 
#define STM32_SRC_PLL3_P   (STM32_SRC_PLL2_R + 1)
 
#define STM32_SRC_PLL3_Q   (STM32_SRC_PLL3_P + 1)
 
#define STM32_SRC_PLL3_R   (STM32_SRC_PLL3_Q + 1)
 
#define STM32_SRC_CKPER   (STM32_SRC_PLL3_R + 1)
 Clock muxes.
 
#define STM32_CLOCK_BUS_AHB1   0x088
 Bus clocks.
 
#define STM32_CLOCK_BUS_AHB2   0x08C
 
#define STM32_CLOCK_BUS_AHB4   0x094
 
#define STM32_CLOCK_BUS_APB1   0x09c
 
#define STM32_CLOCK_BUS_APB1_2   0x0A0
 
#define STM32_CLOCK_BUS_APB2   0x0A4
 
#define STM32_CLOCK_BUS_APB3   0x0A8
 
#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
 
#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3
 
#define STM32_CLOCK_REG_MASK   0xFFU
 
#define STM32_CLOCK_REG_SHIFT   0U
 
#define STM32_CLOCK_SHIFT_MASK   0x1FU
 
#define STM32_CLOCK_SHIFT_SHIFT   8U
 
#define STM32_CLOCK_MASK_MASK   0x7U
 
#define STM32_CLOCK_MASK_SHIFT   13U
 
#define STM32_CLOCK_VAL_MASK   0x7U
 
#define STM32_CLOCK_VAL_SHIFT   16U
 
#define STM32_CLOCK(val, mask, shift, reg)
 STM32H5 clock configuration bit field.
 
#define CCIPR1_REG   0xD8
 RCC_CCIPRx register offset (RM0456.pdf)
 
#define CCIPR2_REG   0xDC
 
#define CCIPR3_REG   0xE0
 
#define CCIPR4_REG   0xE4
 
#define CCIPR5_REG   0xE8
 
#define BDCR_REG   0xF0
 RCC_BDCR register offset.
 
#define USART1_SEL(val)   STM32_CLOCK(val, 7, 0, CCIPR1_REG)
 Device domain clocks selection helpers.
 
#define USART2_SEL(val)   STM32_CLOCK(val, 7, 3, CCIPR1_REG)
 
#define USART3_SEL(val)   STM32_CLOCK(val, 7, 6, CCIPR1_REG)
 
#define USART4_SEL(val)   STM32_CLOCK(val, 7, 9, CCIPR1_REG)
 
#define USART5_SEL(val)   STM32_CLOCK(val, 7, 12, CCIPR1_REG)
 
#define USART6_SEL(val)   STM32_CLOCK(val, 7, 15, CCIPR1_REG)
 
#define USART7_SEL(val)   STM32_CLOCK(val, 7, 18, CCIPR1_REG)
 
#define USART8_SEL(val)   STM32_CLOCK(val, 7, 21, CCIPR1_REG)
 
#define USART9_SEL(val)   STM32_CLOCK(val, 7, 24, CCIPR1_REG)
 
#define USART10_SEL(val)   STM32_CLOCK(val, 7, 27, CCIPR1_REG)
 
#define TIMIC_SEL(val)   STM32_CLOCK(val, 1, 31, CCIPR1_REG)
 
#define USART11_SEL(val)   STM32_CLOCK(val, 7, 0, CCIPR2_REG)
 CCIPR2 devices.
 
#define USART12_SEL(val)   STM32_CLOCK(val, 7, 4, CCIPR2_REG)
 
#define LPTIM1_SEL(val)   STM32_CLOCK(val, 7, 8, CCIPR2_REG)
 
#define LPTIM2_SEL(val)   STM32_CLOCK(val, 7, 12, CCIPR2_REG)
 
#define LPTIM3_SEL(val)   STM32_CLOCK(val, 7, 16, CCIPR2_REG)
 
#define LPTIM4_SEL(val)   STM32_CLOCK(val, 7, 20, CCIPR2_REG)
 
#define LPTIM5_SEL(val)   STM32_CLOCK(val, 7, 24, CCIPR2_REG)
 
#define LPTIM6_SEL(val)   STM32_CLOCK(val, 7, 28, CCIPR2_REG)
 
#define SPI1_SEL(val)   STM32_CLOCK(val, 7, 0, CCIPR3_REG)
 CCIPR3 devices.
 
#define SPI2_SEL(val)   STM32_CLOCK(val, 7, 3, CCIPR3_REG)
 
#define SPI3_SEL(val)   STM32_CLOCK(val, 7, 6, CCIPR3_REG)
 
#define SPI4_SEL(val)   STM32_CLOCK(val, 7, 9, CCIPR3_REG)
 
#define SPI5_SEL(val)   STM32_CLOCK(val, 7, 12, CCIPR3_REG)
 
#define SPI6_SEL(val)   STM32_CLOCK(val, 7, 15, CCIPR2_REG)
 
#define LPUART1_SEL(val)   STM32_CLOCK(val, 7, 24, CCIPR3_REG)
 
#define OCTOSPI1_SEL(val)   STM32_CLOCK(val, 3, 0, CCIPR4_REG)
 CCIPR4 devices.
 
#define SYSTICK_SEL(val)   STM32_CLOCK(val, 3, 2, CCIPR4_REG)
 
#define USB_SEL(val)   STM32_CLOCK(val, 3, 4, CCIPR4_REG)
 
#define SDMMC1_SEL(val)   STM32_CLOCK(val, 1, 6, CCIPR4_REG)
 
#define SDMMC2_SEL(val)   STM32_CLOCK(val, 1, 7, CCIPR4_REG)
 
#define I2C1_SEL(val)   STM32_CLOCK(val, 3, 16, CCIPR4_REG)
 
#define I2C2_SEL(val)   STM32_CLOCK(val, 3, 18, CCIPR4_REG)
 
#define I2C3_SEL(val)   STM32_CLOCK(val, 3, 20, CCIPR4_REG)
 
#define I2C4_SEL(val)   STM32_CLOCK(val, 3, 22, CCIPR4_REG)
 
#define I3C1_SEL(val)   STM32_CLOCK(val, 3, 24, CCIPR4_REG)
 
#define ADCDAC_SEL(val)   STM32_CLOCK(val, 7, 0, CCIPR5_REG)
 CCIPR5 devices.
 
#define DAC_SEL(val)   STM32_CLOCK(val, 1, 3, CCIPR5_REG)
 
#define RNG_SEL(val)   STM32_CLOCK(val, 3, 4, CCIPR5_REG)
 
#define CEC_SEL(val)   STM32_CLOCK(val, 3, 6, CCIPR5_REG)
 
#define FDCAN_SEL(val)   STM32_CLOCK(val, 3, 8, CCIPR5_REG)
 
#define SAI1_SEL(val)   STM32_CLOCK(val, 7, 16, CCIPR5_REG)
 
#define SAI2_SEL(val)   STM32_CLOCK(val, 7, 19, CCIPR5_REG)
 
#define CKPER_SEL(val)   STM32_CLOCK(val, 3, 30, CCIPR5_REG)
 
#define RTC_SEL(val)   STM32_CLOCK(val, 3, 8, BDCR_REG)
 BDCR devices.
 

Macro Definition Documentation

◆ ADCDAC_SEL

#define ADCDAC_SEL (   val)    STM32_CLOCK(val, 7, 0, CCIPR5_REG)

CCIPR5 devices.

◆ BDCR_REG

#define BDCR_REG   0xF0

RCC_BDCR register offset.

◆ CCIPR1_REG

#define CCIPR1_REG   0xD8

RCC_CCIPRx register offset (RM0456.pdf)

◆ CCIPR2_REG

#define CCIPR2_REG   0xDC

◆ CCIPR3_REG

#define CCIPR3_REG   0xE0

◆ CCIPR4_REG

#define CCIPR4_REG   0xE4

◆ CCIPR5_REG

#define CCIPR5_REG   0xE8

◆ CEC_SEL

#define CEC_SEL (   val)    STM32_CLOCK(val, 3, 6, CCIPR5_REG)

◆ CKPER_SEL

#define CKPER_SEL (   val)    STM32_CLOCK(val, 3, 30, CCIPR5_REG)

◆ DAC_SEL

#define DAC_SEL (   val)    STM32_CLOCK(val, 1, 3, CCIPR5_REG)

◆ FDCAN_SEL

#define FDCAN_SEL (   val)    STM32_CLOCK(val, 3, 8, CCIPR5_REG)

◆ I2C1_SEL

#define I2C1_SEL (   val)    STM32_CLOCK(val, 3, 16, CCIPR4_REG)

◆ I2C2_SEL

#define I2C2_SEL (   val)    STM32_CLOCK(val, 3, 18, CCIPR4_REG)

◆ I2C3_SEL

#define I2C3_SEL (   val)    STM32_CLOCK(val, 3, 20, CCIPR4_REG)

◆ I2C4_SEL

#define I2C4_SEL (   val)    STM32_CLOCK(val, 3, 22, CCIPR4_REG)

◆ I3C1_SEL

#define I3C1_SEL (   val)    STM32_CLOCK(val, 3, 24, CCIPR4_REG)

◆ LPTIM1_SEL

#define LPTIM1_SEL (   val)    STM32_CLOCK(val, 7, 8, CCIPR2_REG)

◆ LPTIM2_SEL

#define LPTIM2_SEL (   val)    STM32_CLOCK(val, 7, 12, CCIPR2_REG)

◆ LPTIM3_SEL

#define LPTIM3_SEL (   val)    STM32_CLOCK(val, 7, 16, CCIPR2_REG)

◆ LPTIM4_SEL

#define LPTIM4_SEL (   val)    STM32_CLOCK(val, 7, 20, CCIPR2_REG)

◆ LPTIM5_SEL

#define LPTIM5_SEL (   val)    STM32_CLOCK(val, 7, 24, CCIPR2_REG)

◆ LPTIM6_SEL

#define LPTIM6_SEL (   val)    STM32_CLOCK(val, 7, 28, CCIPR2_REG)

◆ LPUART1_SEL

#define LPUART1_SEL (   val)    STM32_CLOCK(val, 7, 24, CCIPR3_REG)

◆ OCTOSPI1_SEL

#define OCTOSPI1_SEL (   val)    STM32_CLOCK(val, 3, 0, CCIPR4_REG)

CCIPR4 devices.

◆ RNG_SEL

#define RNG_SEL (   val)    STM32_CLOCK(val, 3, 4, CCIPR5_REG)

◆ RTC_SEL

#define RTC_SEL (   val)    STM32_CLOCK(val, 3, 8, BDCR_REG)

BDCR devices.

◆ SAI1_SEL

#define SAI1_SEL (   val)    STM32_CLOCK(val, 7, 16, CCIPR5_REG)

◆ SAI2_SEL

#define SAI2_SEL (   val)    STM32_CLOCK(val, 7, 19, CCIPR5_REG)

◆ SDMMC1_SEL

#define SDMMC1_SEL (   val)    STM32_CLOCK(val, 1, 6, CCIPR4_REG)

◆ SDMMC2_SEL

#define SDMMC2_SEL (   val)    STM32_CLOCK(val, 1, 7, CCIPR4_REG)

◆ SPI1_SEL

#define SPI1_SEL (   val)    STM32_CLOCK(val, 7, 0, CCIPR3_REG)

CCIPR3 devices.

◆ SPI2_SEL

#define SPI2_SEL (   val)    STM32_CLOCK(val, 7, 3, CCIPR3_REG)

◆ SPI3_SEL

#define SPI3_SEL (   val)    STM32_CLOCK(val, 7, 6, CCIPR3_REG)

◆ SPI4_SEL

#define SPI4_SEL (   val)    STM32_CLOCK(val, 7, 9, CCIPR3_REG)

◆ SPI5_SEL

#define SPI5_SEL (   val)    STM32_CLOCK(val, 7, 12, CCIPR3_REG)

◆ SPI6_SEL

#define SPI6_SEL (   val)    STM32_CLOCK(val, 7, 15, CCIPR2_REG)

◆ STM32_CLOCK

#define STM32_CLOCK (   val,
  mask,
  shift,
  reg 
)
Value:
#define STM32_CLOCK_SHIFT_SHIFT
Definition stm32h5_clock.h:52
#define STM32_CLOCK_REG_SHIFT
Definition stm32h5_clock.h:50
#define STM32_CLOCK_REG_MASK
Definition stm32h5_clock.h:49
#define STM32_CLOCK_MASK_MASK
Definition stm32h5_clock.h:53
#define STM32_CLOCK_VAL_MASK
Definition stm32h5_clock.h:55
#define STM32_CLOCK_MASK_SHIFT
Definition stm32h5_clock.h:54
#define STM32_CLOCK_VAL_SHIFT
Definition stm32h5_clock.h:56
#define STM32_CLOCK_SHIFT_MASK
Definition stm32h5_clock.h:51

STM32H5 clock configuration bit field.

  • reg (1/2/3/4/5) [ 0 : 7 ]
  • shift (0..31) [ 8 : 12 ]
  • mask (0x1, 0x3, 0x7) [ 13 : 15 ]
  • val (0..7) [ 16 : 18 ]
Parameters
regRCC_CCIPRx register offset
shiftPosition within RCC_CCIPRx.
maskMask for the RCC_CCIPRx field.
valClock value (0, 1, ... 7).

◆ STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x088

Bus clocks.

◆ STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x08C

◆ STM32_CLOCK_BUS_AHB4

#define STM32_CLOCK_BUS_AHB4   0x094

◆ STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x09c

◆ STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x0A0

◆ STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x0A4

◆ STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x0A8

◆ STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

◆ STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   13U

◆ STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFU

◆ STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

◆ STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

◆ STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   8U

◆ STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

◆ STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   16U

◆ STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3

◆ STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

◆ STM32_SRC_CKPER

#define STM32_SRC_CKPER   (STM32_SRC_PLL3_R + 1)

Clock muxes.

◆ STM32_SRC_CSI

#define STM32_SRC_CSI   (STM32_SRC_HSE + 1)

◆ STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

◆ STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_CSI + 1)

◆ STM32_SRC_HSI48

#define STM32_SRC_HSI48   (STM32_SRC_HSI + 1)

◆ STM32_SRC_PLL1_P

#define STM32_SRC_PLL1_P   (STM32_SRC_HSI48 + 1)

PLL outputs.

◆ STM32_SRC_PLL1_Q

#define STM32_SRC_PLL1_Q   (STM32_SRC_PLL1_P + 1)

◆ STM32_SRC_PLL1_R

#define STM32_SRC_PLL1_R   (STM32_SRC_PLL1_Q + 1)

◆ STM32_SRC_PLL2_P

#define STM32_SRC_PLL2_P   (STM32_SRC_PLL1_R + 1)

◆ STM32_SRC_PLL2_Q

#define STM32_SRC_PLL2_Q   (STM32_SRC_PLL2_P + 1)

◆ STM32_SRC_PLL2_R

#define STM32_SRC_PLL2_R   (STM32_SRC_PLL2_Q + 1)

◆ STM32_SRC_PLL3_P

#define STM32_SRC_PLL3_P   (STM32_SRC_PLL2_R + 1)

◆ STM32_SRC_PLL3_Q

#define STM32_SRC_PLL3_Q   (STM32_SRC_PLL3_P + 1)

◆ STM32_SRC_PLL3_R

#define STM32_SRC_PLL3_R   (STM32_SRC_PLL3_Q + 1)

◆ SYSTICK_SEL

#define SYSTICK_SEL (   val)    STM32_CLOCK(val, 3, 2, CCIPR4_REG)

◆ TIMIC_SEL

#define TIMIC_SEL (   val)    STM32_CLOCK(val, 1, 31, CCIPR1_REG)

◆ USART10_SEL

#define USART10_SEL (   val)    STM32_CLOCK(val, 7, 27, CCIPR1_REG)

◆ USART11_SEL

#define USART11_SEL (   val)    STM32_CLOCK(val, 7, 0, CCIPR2_REG)

CCIPR2 devices.

◆ USART12_SEL

#define USART12_SEL (   val)    STM32_CLOCK(val, 7, 4, CCIPR2_REG)

◆ USART1_SEL

#define USART1_SEL (   val)    STM32_CLOCK(val, 7, 0, CCIPR1_REG)

Device domain clocks selection helpers.

CCIPR1 devices

◆ USART2_SEL

#define USART2_SEL (   val)    STM32_CLOCK(val, 7, 3, CCIPR1_REG)

◆ USART3_SEL

#define USART3_SEL (   val)    STM32_CLOCK(val, 7, 6, CCIPR1_REG)

◆ USART4_SEL

#define USART4_SEL (   val)    STM32_CLOCK(val, 7, 9, CCIPR1_REG)

◆ USART5_SEL

#define USART5_SEL (   val)    STM32_CLOCK(val, 7, 12, CCIPR1_REG)

◆ USART6_SEL

#define USART6_SEL (   val)    STM32_CLOCK(val, 7, 15, CCIPR1_REG)

◆ USART7_SEL

#define USART7_SEL (   val)    STM32_CLOCK(val, 7, 18, CCIPR1_REG)

◆ USART8_SEL

#define USART8_SEL (   val)    STM32_CLOCK(val, 7, 21, CCIPR1_REG)

◆ USART9_SEL

#define USART9_SEL (   val)    STM32_CLOCK(val, 7, 24, CCIPR1_REG)

◆ USB_SEL

#define USB_SEL (   val)    STM32_CLOCK(val, 3, 4, CCIPR4_REG)