Zephyr Project API
4.1.0
A Scalable Open Source RTOS
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stm32l0_clock.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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#define STM32_CLOCK_BUS_IOP 0x02c
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#define STM32_CLOCK_BUS_AHB1 0x030
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#define STM32_CLOCK_BUS_APB2 0x034
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#define STM32_CLOCK_BUS_APB1 0x038
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
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/* RM0367, ยง7.3.20 Clock configuration register (RCC_CCIPR) */
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/* defined in stm32_common_clocks.h */
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/* Low speed clocks defined in stm32_common_clocks.h */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
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#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)
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#define STM32_SRC_PCLK (STM32_SRC_HSI48 + 1)
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#define CCIPR_REG 0x4C
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#define CSR_REG 0x50
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#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
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#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
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#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
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#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
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#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
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#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
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#define HSI48_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 26, CCIPR_REG)
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CSR_REG)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */
stm32_common_clocks.h
include
zephyr
dt-bindings
clock
stm32l0_clock.h
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