Zephyr Project API 4.1.0
A Scalable Open Source RTOS
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stm32n6_clock.h
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1/*
2 * Copyright (c) 2024 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
7#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
8
10
13/* RM0468, Table 56 Kernel clock distribution summary */
14
16/* defined in stm32_common_clocks.h */
18#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
19#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
20#define STM32_SRC_MSI (STM32_SRC_HSI + 1)
22#define STM32_SRC_PLL1 (STM32_SRC_MSI + 1)
23#define STM32_SRC_PLL2 (STM32_SRC_PLL1 + 1)
24#define STM32_SRC_PLL3 (STM32_SRC_PLL2 + 1)
25#define STM32_SRC_PLL4 (STM32_SRC_PLL3 + 1)
27#define STM32_SRC_CKPER (STM32_SRC_PLL4 + 1)
28#define STM32_SRC_IC1 (STM32_SRC_CKPER + 1)
29#define STM32_SRC_IC2 (STM32_SRC_IC1 + 1)
30#define STM32_SRC_IC3 (STM32_SRC_IC2 + 1)
31#define STM32_SRC_IC4 (STM32_SRC_IC3 + 1)
32#define STM32_SRC_IC5 (STM32_SRC_IC4 + 1)
33#define STM32_SRC_IC6 (STM32_SRC_IC5 + 1)
34#define STM32_SRC_IC7 (STM32_SRC_IC6 + 1)
35#define STM32_SRC_IC8 (STM32_SRC_IC7 + 1)
36#define STM32_SRC_IC9 (STM32_SRC_IC8 + 1)
37#define STM32_SRC_IC10 (STM32_SRC_IC9 + 1)
38#define STM32_SRC_IC11 (STM32_SRC_IC10 + 1)
39#define STM32_SRC_IC12 (STM32_SRC_IC11 + 1)
40#define STM32_SRC_IC13 (STM32_SRC_IC12 + 1)
41#define STM32_SRC_IC14 (STM32_SRC_IC13 + 1)
42#define STM32_SRC_IC15 (STM32_SRC_IC14 + 1)
43#define STM32_SRC_IC16 (STM32_SRC_IC15 + 1)
44#define STM32_SRC_IC17 (STM32_SRC_IC16 + 1)
45#define STM32_SRC_IC18 (STM32_SRC_IC17 + 1)
46#define STM32_SRC_IC19 (STM32_SRC_IC18 + 1)
47#define STM32_SRC_IC20 (STM32_SRC_IC19 + 1)
48
50#define STM32_CLOCK_BUS_AHB1 0x250
51#define STM32_CLOCK_BUS_AHB2 0x254
52#define STM32_CLOCK_BUS_AHB3 0x258
53#define STM32_CLOCK_BUS_AHB4 0x25C
54#define STM32_CLOCK_BUS_AHB5 0x260
55#define STM32_CLOCK_BUS_APB1 0x264
56#define STM32_CLOCK_BUS_APB1_2 0x268
57#define STM32_CLOCK_BUS_APB2 0x26C
58#define STM32_CLOCK_BUS_APB3 0x270
59#define STM32_CLOCK_BUS_APB4 0x274
60#define STM32_CLOCK_BUS_APB4_2 0x278
61#define STM32_CLOCK_BUS_APB5 0x27C
62
63#define STM32_CLOCK_LP_BUS_SHIFT 0x40
64
65#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
66#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB5
67
69#define CCIPR1_REG 0x144
70#define CCIPR2_REG 0x148
71#define CCIPR3_REG 0x14C
72#define CCIPR4_REG 0x150
73#define CCIPR5_REG 0x154
74#define CCIPR6_REG 0x158
75#define CCIPR7_REG 0x15C
76#define CCIPR8_REG 0x160
77#define CCIPR9_REG 0x164
78#define CCIPR12_REG 0x170
79#define CCIPR13_REG 0x174
80#define CCIPR14_REG 0x178
81
84#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG)
85#define ADC12_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR1_REG)
86#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)
88#define ETH1PTP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
89#define ETH1CLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
90#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG)
91#define ETH1REFCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG)
92#define ETH1GTXCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR2_REG)
94#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
95#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR3_REG)
97#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR4_REG)
98#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR4_REG)
99#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR4_REG)
100#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR4_REG)
101#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR4_REG)
102#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR4_REG)
103#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR4_REG)
105#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR5_REG)
106#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR5_REG)
107#define MDF1SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR5_REG)
109#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR6_REG)
110#define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR6_REG)
111#define XSPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR6_REG)
112#define OTGPHY1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR6_REG)
113#define OTGPHY1CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR6_REG)
114#define OTGPHY2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR6_REG)
115#define OTGPHY2CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR6_REG)
117#define PER_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR7_REG)
118#define PSSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR7_REG)
119#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR7_REG)
120#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR7_REG)
121#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR7_REG)
123#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR8_REG)
124#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR8_REG)
126#define SPDIFRX1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR9_REG)
127#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR9_REG)
128#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR9_REG)
129#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR9_REG)
130#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR9_REG)
131#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR9_REG)
132#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR9_REG)
134#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR12_REG)
135#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR12_REG)
136#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR12_REG)
137#define LPTIM4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR12_REG)
138#define LPTIM5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR12_REG)
140#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR13_REG)
141#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR13_REG)
142#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR13_REG)
143#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR13_REG)
144#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR13_REG)
145#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR13_REG)
146#define UART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR13_REG)
147#define UART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, CCIPR13_REG)
149#define UART9_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR14_REG)
150#define USART10_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR14_REG)
151#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR14_REG)
152
154#define ICxCFGR_REG(ic) (0xC4 + ((ic) - 1) * 4)
155
157#define ICx_PLLy_SEL(ic, pll) STM32_DT_CLOCK_SELECT((pll) - 1, 3, 28, ICxCFGR_REG(ic))
158
160#define CFGR1_REG 0x20
161
163#define CPU_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR1_REG)
164
165#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_ */