Zephyr Project API
4.1.0
A Scalable Open Source RTOS
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stm32n6_clock.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
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#include "
stm32_common_clocks.h
"
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/* RM0468, Table 56 Kernel clock distribution summary */
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/* defined in stm32_common_clocks.h */
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#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
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#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
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#define STM32_SRC_MSI (STM32_SRC_HSI + 1)
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#define STM32_SRC_PLL1 (STM32_SRC_MSI + 1)
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#define STM32_SRC_PLL2 (STM32_SRC_PLL1 + 1)
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#define STM32_SRC_PLL3 (STM32_SRC_PLL2 + 1)
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#define STM32_SRC_PLL4 (STM32_SRC_PLL3 + 1)
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#define STM32_SRC_CKPER (STM32_SRC_PLL4 + 1)
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#define STM32_SRC_IC1 (STM32_SRC_CKPER + 1)
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#define STM32_SRC_IC2 (STM32_SRC_IC1 + 1)
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#define STM32_SRC_IC3 (STM32_SRC_IC2 + 1)
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#define STM32_SRC_IC4 (STM32_SRC_IC3 + 1)
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#define STM32_SRC_IC5 (STM32_SRC_IC4 + 1)
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#define STM32_SRC_IC6 (STM32_SRC_IC5 + 1)
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#define STM32_SRC_IC7 (STM32_SRC_IC6 + 1)
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#define STM32_SRC_IC8 (STM32_SRC_IC7 + 1)
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#define STM32_SRC_IC9 (STM32_SRC_IC8 + 1)
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#define STM32_SRC_IC10 (STM32_SRC_IC9 + 1)
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#define STM32_SRC_IC11 (STM32_SRC_IC10 + 1)
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#define STM32_SRC_IC12 (STM32_SRC_IC11 + 1)
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#define STM32_SRC_IC13 (STM32_SRC_IC12 + 1)
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#define STM32_SRC_IC14 (STM32_SRC_IC13 + 1)
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#define STM32_SRC_IC15 (STM32_SRC_IC14 + 1)
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#define STM32_SRC_IC16 (STM32_SRC_IC15 + 1)
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#define STM32_SRC_IC17 (STM32_SRC_IC16 + 1)
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#define STM32_SRC_IC18 (STM32_SRC_IC17 + 1)
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#define STM32_SRC_IC19 (STM32_SRC_IC18 + 1)
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#define STM32_SRC_IC20 (STM32_SRC_IC19 + 1)
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#define STM32_CLOCK_BUS_AHB1 0x250
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#define STM32_CLOCK_BUS_AHB2 0x254
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#define STM32_CLOCK_BUS_AHB3 0x258
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#define STM32_CLOCK_BUS_AHB4 0x25C
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#define STM32_CLOCK_BUS_AHB5 0x260
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#define STM32_CLOCK_BUS_APB1 0x264
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#define STM32_CLOCK_BUS_APB1_2 0x268
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#define STM32_CLOCK_BUS_APB2 0x26C
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#define STM32_CLOCK_BUS_APB3 0x270
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#define STM32_CLOCK_BUS_APB4 0x274
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#define STM32_CLOCK_BUS_APB4_2 0x278
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#define STM32_CLOCK_BUS_APB5 0x27C
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#define STM32_CLOCK_LP_BUS_SHIFT 0x40
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#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
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#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB5
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#define CCIPR1_REG 0x144
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#define CCIPR2_REG 0x148
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#define CCIPR3_REG 0x14C
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#define CCIPR4_REG 0x150
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#define CCIPR5_REG 0x154
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#define CCIPR6_REG 0x158
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#define CCIPR7_REG 0x15C
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#define CCIPR8_REG 0x160
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#define CCIPR9_REG 0x164
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#define CCIPR12_REG 0x170
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#define CCIPR13_REG 0x174
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#define CCIPR14_REG 0x178
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#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG)
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#define ADC12_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR1_REG)
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#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)
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#define ETH1PTP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
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#define ETH1CLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
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#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG)
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#define ETH1REFCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG)
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#define ETH1GTXCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR2_REG)
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#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
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#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR3_REG)
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#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR4_REG)
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#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR4_REG)
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#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR4_REG)
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#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR4_REG)
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#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR4_REG)
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#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR4_REG)
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#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR4_REG)
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#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR5_REG)
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#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR5_REG)
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#define MDF1SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR5_REG)
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#define XSPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR6_REG)
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#define XSPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR6_REG)
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#define XSPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR6_REG)
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#define OTGPHY1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR6_REG)
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#define OTGPHY1CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR6_REG)
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#define OTGPHY2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR6_REG)
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#define OTGPHY2CKREF_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR6_REG)
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#define PER_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR7_REG)
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#define PSSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR7_REG)
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#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR7_REG)
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#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR7_REG)
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#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR7_REG)
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#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR8_REG)
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#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR8_REG)
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#define SPDIFRX1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR9_REG)
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#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR9_REG)
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#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR9_REG)
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#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR9_REG)
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#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR9_REG)
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#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR9_REG)
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#define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR9_REG)
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#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR12_REG)
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#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR12_REG)
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#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR12_REG)
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#define LPTIM4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR12_REG)
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#define LPTIM5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR12_REG)
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#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR13_REG)
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#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR13_REG)
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#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR13_REG)
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#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR13_REG)
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#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR13_REG)
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#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR13_REG)
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#define UART7_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR13_REG)
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#define UART8_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, CCIPR13_REG)
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#define UART9_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR14_REG)
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#define USART10_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR14_REG)
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#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR14_REG)
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#define ICxCFGR_REG(ic) (0xC4 + ((ic) - 1) * 4)
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#define ICx_PLLy_SEL(ic, pll) STM32_DT_CLOCK_SELECT((pll) - 1, 3, 28, ICxCFGR_REG(ic))
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#define CFGR1_REG 0x20
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#define CPU_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR1_REG)
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#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_ */
stm32_common_clocks.h
include
zephyr
dt-bindings
clock
stm32n6_clock.h
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