stm32n6_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_SRC_HSE   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_HSI   (STM32_SRC_HSE + 1)
#define	STM32_SRC_MSI   (STM32_SRC_HSI + 1)
#define	STM32_SRC_PLL1   (STM32_SRC_MSI + 1)
	PLL outputs.
#define	STM32_SRC_PLL2   (STM32_SRC_PLL1 + 1)
#define	STM32_SRC_PLL3   (STM32_SRC_PLL2 + 1)
#define	STM32_SRC_PLL4   (STM32_SRC_PLL3 + 1)
#define	STM32_SRC_CKPER   (STM32_SRC_PLL4 + 1)
	Clock muxes.
#define	STM32_SRC_IC1   (STM32_SRC_CKPER + 1)
#define	STM32_SRC_IC2   (STM32_SRC_IC1 + 1)
#define	STM32_SRC_IC3   (STM32_SRC_IC2 + 1)
#define	STM32_SRC_IC4   (STM32_SRC_IC3 + 1)
#define	STM32_SRC_IC5   (STM32_SRC_IC4 + 1)
#define	STM32_SRC_IC6   (STM32_SRC_IC5 + 1)
#define	STM32_SRC_IC7   (STM32_SRC_IC6 + 1)
#define	STM32_SRC_IC8   (STM32_SRC_IC7 + 1)
#define	STM32_SRC_IC9   (STM32_SRC_IC8 + 1)
#define	STM32_SRC_IC10   (STM32_SRC_IC9 + 1)
#define	STM32_SRC_IC11   (STM32_SRC_IC10 + 1)
#define	STM32_SRC_IC12   (STM32_SRC_IC11 + 1)
#define	STM32_SRC_IC13   (STM32_SRC_IC12 + 1)
#define	STM32_SRC_IC14   (STM32_SRC_IC13 + 1)
#define	STM32_SRC_IC15   (STM32_SRC_IC14 + 1)
#define	STM32_SRC_IC16   (STM32_SRC_IC15 + 1)
#define	STM32_SRC_IC17   (STM32_SRC_IC16 + 1)
#define	STM32_SRC_IC18   (STM32_SRC_IC17 + 1)
#define	STM32_SRC_IC19   (STM32_SRC_IC18 + 1)
#define	STM32_SRC_IC20   (STM32_SRC_IC19 + 1)
#define	STM32_CLOCK_BUS_AHB1   0x250
	Bus clocks.
#define	STM32_CLOCK_BUS_AHB2   0x254
#define	STM32_CLOCK_BUS_AHB3   0x258
#define	STM32_CLOCK_BUS_AHB4   0x25C
#define	STM32_CLOCK_BUS_AHB5   0x260
#define	STM32_CLOCK_BUS_APB1   0x264
#define	STM32_CLOCK_BUS_APB1_2   0x268
#define	STM32_CLOCK_BUS_APB2   0x26C
#define	STM32_CLOCK_BUS_APB3   0x270
#define	STM32_CLOCK_BUS_APB4   0x274
#define	STM32_CLOCK_BUS_APB4_2   0x278
#define	STM32_CLOCK_BUS_APB5   0x27C
#define	STM32_CLOCK_LP_BUS_SHIFT   0x40
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB5
#define	STM32_CLOCK_REG_MASK   0xFFFU
#define	STM32_CLOCK_REG_SHIFT   0U
#define	STM32_CLOCK_SHIFT_MASK   0x1FU
#define	STM32_CLOCK_SHIFT_SHIFT   12U
#define	STM32_CLOCK_MASK_MASK   0x7U
#define	STM32_CLOCK_MASK_SHIFT   17U
#define	STM32_CLOCK_VAL_MASK   0x7U
#define	STM32_CLOCK_VAL_SHIFT   20U
#define	STM32_DOMAIN_CLOCK(val, mask, shift, reg)
	STM32U5 clock configuration bit field.
#define	CCIPR1_REG   0x144
	RCC_CCIPRx register offset (RM0468.pdf)
#define	CCIPR2_REG   0x148
#define	CCIPR3_REG   0x14C
#define	CCIPR4_REG   0x150
#define	CCIPR5_REG   0x154
#define	CCIPR6_REG   0x158
#define	CCIPR7_REG   0x15C
#define	CCIPR8_REG   0x160
#define	CCIPR9_REG   0x164
#define	CCIPR12_REG   0x170
#define	CCIPR13_REG   0x174
#define	CCIPR14_REG   0x178
#define	ADF1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR1_REG)
	Device domain clocks selection helpers.
#define	ADC12_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR1_REG)
#define	DCMIPP_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 20, CCIPR1_REG)
#define	ETH1PTP_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR2_REG)
	CCIPR2 devices.
#define	ETH1CLK_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 12, CCIPR2_REG)
#define	ETH1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR2_REG)
#define	ETH1REFCLK_SEL(val)   STM32_DOMAIN_CLOCK((val), 1, 20, CCIPR2_REG)
#define	ETH1GTXCLK_SEL(val)   STM32_DOMAIN_CLOCK((val), 1, 24, CCIPR2_REG)
#define	FDCAN_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR3_REG)
	CCIPR3 devices.
#define	FMC_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR3_REG)
#define	I2C1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR4_REG)
	CCIPR4 devices.
#define	I2C2_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR4_REG)
#define	I2C3_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR4_REG)
#define	I2C4_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR4_REG)
#define	I3C1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR4_REG)
#define	I3C2_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR4_REG)
#define	LTDC_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 24, CCIPR4_REG)
#define	MCO1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR5_REG)
	CCIPR5 devices.
#define	MCO2_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR5_REG)
#define	MDF1SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR5_REG)
#define	XSPI1_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR6_REG)
	CCIPR6 devices.
#define	XSPI2_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR6_REG)
#define	XSPI3_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 8, CCIPR6_REG)
#define	OTGPHY1_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 12, CCIPR6_REG)
#define	OTGPHY1CKREF_SEL(val)   STM32_DOMAIN_CLOCK((val), 1, 16, CCIPR6_REG)
#define	OTGPHY2_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 20, CCIPR6_REG)
#define	OTGPHY2CKREF_SEL(val)   STM32_DOMAIN_CLOCK((val), 1, 24, CCIPR6_REG)
#define	PER_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR7_REG)
	CCIPR7 devices.
#define	PSSI_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR7_REG)
#define	RTC_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 8, CCIPR7_REG)
#define	SAI1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR7_REG)
#define	SAI2_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR7_REG)
#define	SDMMC1_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR8_REG)
	CCIPR8 devices.
#define	SDMMC2_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR8_REG)
#define	SPDIFRX1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR9_REG)
	CCIPR9 devices.
#define	SPI1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR9_REG)
#define	SPI2_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR9_REG)
#define	SPI3_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR9_REG)
#define	SPI4_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR9_REG)
#define	SPI5_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR9_REG)
#define	SPI6_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR9_REG)
#define	LPTIM1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR12_REG)
	CCIPR12 devices.
#define	LPTIM2_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR12_REG)
#define	LPTIM3_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR12_REG)
#define	LPTIM4_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR12_REG)
#define	LPTIM5_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR12_REG)
#define	USART1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR13_REG)
	CCIPR13 devices.
#define	USART2_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR13_REG)
#define	USART3_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR13_REG)
#define	UART4_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR13_REG)
#define	UART5_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR13_REG)
#define	USART6_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR13_REG)
#define	UART7_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR13_REG)
#define	UART8_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 28, CCIPR13_REG)
#define	UART9_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR14_REG)
	CCIPR14 devices.
#define	USART10_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR14_REG)
#define	LPUART1_SEL(val)   STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR14_REG)
#define	ICxCFGR_REG(ic)   (0xC4 + ((ic) - 1) * 4)
	RCC_ICxCFGR register offset (RM0468.pdf)
#define	ICx_PLLy_SEL(ic, pll)   STM32_DOMAIN_CLOCK((pll) - 1, 3, 28, ICxCFGR_REG(ic))
	Divider ICx source selection.
#define	CFGR1_REG   0x20
	RCC_CFGR1 register offset (RM0468.pdf)
#define	CPU_SEL(val)   STM32_DOMAIN_CLOCK((val), 3, 16, CFGR1_REG)
	CPU clock switch selection.

Macro Definition Documentation

ADC12_SEL

#define ADC12_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR1_REG)

ADF1_SEL

#define ADF1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR1_REG)

Device domain clocks selection helpers.

CCIPR1 devices

CCIPR12_REG

#define CCIPR12_REG   0x170

CCIPR13_REG

#define CCIPR13_REG   0x174

CCIPR14_REG

#define CCIPR14_REG   0x178

CCIPR1_REG

#define CCIPR1_REG   0x144

RCC_CCIPRx register offset (RM0468.pdf)

CCIPR2_REG

#define CCIPR2_REG   0x148

CCIPR3_REG

#define CCIPR3_REG   0x14C

CCIPR4_REG

#define CCIPR4_REG   0x150

CCIPR5_REG

#define CCIPR5_REG   0x154

CCIPR6_REG

#define CCIPR6_REG   0x158

CCIPR7_REG

#define CCIPR7_REG   0x15C

CCIPR8_REG

#define CCIPR8_REG   0x160

CCIPR9_REG

#define CCIPR9_REG   0x164

CFGR1_REG

#define CFGR1_REG   0x20

RCC_CFGR1 register offset (RM0468.pdf)

CPU_SEL

#define CPU_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 16, CFGR1_REG)

CPU clock switch selection.

DCMIPP_SEL

#define DCMIPP_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 20, CCIPR1_REG)

ETH1_SEL

#define ETH1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR2_REG)

ETH1CLK_SEL

#define ETH1CLK_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 12, CCIPR2_REG)

ETH1GTXCLK_SEL

#define ETH1GTXCLK_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 1, 24, CCIPR2_REG)

ETH1PTP_SEL

#define ETH1PTP_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR2_REG)

CCIPR2 devices.

ETH1REFCLK_SEL

#define ETH1REFCLK_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 1, 20, CCIPR2_REG)

FDCAN_SEL

#define FDCAN_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR3_REG)

CCIPR3 devices.

FMC_SEL

#define FMC_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR3_REG)

I2C1_SEL

#define I2C1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR4_REG)

CCIPR4 devices.

I2C2_SEL

#define I2C2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR4_REG)

I2C3_SEL

#define I2C3_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR4_REG)

I2C4_SEL

#define I2C4_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR4_REG)

I3C1_SEL

#define I3C1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR4_REG)

I3C2_SEL

#define I3C2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR4_REG)

ICx_PLLy_SEL

#define ICx_PLLy_SEL	(		ic,
			pll
	)		STM32_DOMAIN_CLOCK((pll) - 1, 3, 28, ICxCFGR_REG(ic))

Divider ICx source selection.

ICxCFGR_REG

#define ICxCFGR_REG

(

ic

)

(0xC4 + ((ic) - 1) * 4)

RCC_ICxCFGR register offset (RM0468.pdf)

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR12_REG)

CCIPR12 devices.

LPTIM2_SEL

#define LPTIM2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR12_REG)

LPTIM3_SEL

#define LPTIM3_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR12_REG)

LPTIM4_SEL

#define LPTIM4_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR12_REG)

LPTIM5_SEL

#define LPTIM5_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR12_REG)

LPUART1_SEL

#define LPUART1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR14_REG)

LTDC_SEL

#define LTDC_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 24, CCIPR4_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR5_REG)

CCIPR5 devices.

MCO2_SEL

#define MCO2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR5_REG)

MDF1SEL

#define MDF1SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR5_REG)

OTGPHY1_SEL

#define OTGPHY1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 12, CCIPR6_REG)

OTGPHY1CKREF_SEL

#define OTGPHY1CKREF_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 1, 16, CCIPR6_REG)

OTGPHY2_SEL

#define OTGPHY2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 20, CCIPR6_REG)

OTGPHY2CKREF_SEL

#define OTGPHY2CKREF_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 1, 24, CCIPR6_REG)

PER_SEL

#define PER_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR7_REG)

CCIPR7 devices.

PSSI_SEL

#define PSSI_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR7_REG)

RTC_SEL

#define RTC_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 8, CCIPR7_REG)

SAI1_SEL

#define SAI1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR7_REG)

SAI2_SEL

#define SAI2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR7_REG)

SDMMC1_SEL

#define SDMMC1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR8_REG)

CCIPR8 devices.

SDMMC2_SEL

#define SDMMC2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR8_REG)

SPDIFRX1_SEL

#define SPDIFRX1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR9_REG)

CCIPR9 devices.

SPI1_SEL

#define SPI1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR9_REG)

SPI2_SEL

#define SPI2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR9_REG)

SPI3_SEL

#define SPI3_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR9_REG)

SPI4_SEL

#define SPI4_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR9_REG)

SPI5_SEL

#define SPI5_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR9_REG)

SPI6_SEL

#define SPI6_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR9_REG)

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x250

Bus clocks.

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x254

STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x258

STM32_CLOCK_BUS_AHB4

#define STM32_CLOCK_BUS_AHB4   0x25C

STM32_CLOCK_BUS_AHB5

#define STM32_CLOCK_BUS_AHB5   0x260

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x264

STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x268

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x26C

STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x270

STM32_CLOCK_BUS_APB4

#define STM32_CLOCK_BUS_APB4   0x274

STM32_CLOCK_BUS_APB4_2

#define STM32_CLOCK_BUS_APB4_2   0x278

STM32_CLOCK_BUS_APB5

#define STM32_CLOCK_BUS_APB5   0x27C

STM32_CLOCK_LP_BUS_SHIFT

#define STM32_CLOCK_LP_BUS_SHIFT   0x40

STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   0x7U

STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   17U

STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   0xFFFU

STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   0U

STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   0x1FU

STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   12U

STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   0x7U

STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   20U

STM32_DOMAIN_CLOCK

#define STM32_DOMAIN_CLOCK	(		val,
			mask,
			shift,
			reg
	)

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32U5 clock configuration bit field.

• reg (1/2/3) [ 0 : 11 ]
• shift (0..31) [ 12 : 16 ]
• mask (0x1, 0x3, 0x7) [ 17 : 19 ]
• val (0..7) [ 20 : 22 ]

Parameters

reg	RCC_CCIPRx register offset
shift	Position within RCC_CCIPRx.
mask	Mask for the RCC_CCIPRx field.
val	Clock value (0, 1, ... 7).

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB5

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_CKPER

#define STM32_SRC_CKPER   (STM32_SRC_PLL4 + 1)

Clock muxes.

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_HSE + 1)

STM32_SRC_IC1

#define STM32_SRC_IC1   (STM32_SRC_CKPER + 1)

STM32_SRC_IC10

#define STM32_SRC_IC10   (STM32_SRC_IC9 + 1)

STM32_SRC_IC11

#define STM32_SRC_IC11   (STM32_SRC_IC10 + 1)

STM32_SRC_IC12

#define STM32_SRC_IC12   (STM32_SRC_IC11 + 1)

STM32_SRC_IC13

#define STM32_SRC_IC13   (STM32_SRC_IC12 + 1)

STM32_SRC_IC14

#define STM32_SRC_IC14   (STM32_SRC_IC13 + 1)

STM32_SRC_IC15

#define STM32_SRC_IC15   (STM32_SRC_IC14 + 1)

STM32_SRC_IC16

#define STM32_SRC_IC16   (STM32_SRC_IC15 + 1)

STM32_SRC_IC17

#define STM32_SRC_IC17   (STM32_SRC_IC16 + 1)

STM32_SRC_IC18

#define STM32_SRC_IC18   (STM32_SRC_IC17 + 1)

STM32_SRC_IC19

#define STM32_SRC_IC19   (STM32_SRC_IC18 + 1)

STM32_SRC_IC2

#define STM32_SRC_IC2   (STM32_SRC_IC1 + 1)

STM32_SRC_IC20

#define STM32_SRC_IC20   (STM32_SRC_IC19 + 1)

STM32_SRC_IC3

#define STM32_SRC_IC3   (STM32_SRC_IC2 + 1)

STM32_SRC_IC4

#define STM32_SRC_IC4   (STM32_SRC_IC3 + 1)

STM32_SRC_IC5

#define STM32_SRC_IC5   (STM32_SRC_IC4 + 1)

STM32_SRC_IC6

#define STM32_SRC_IC6   (STM32_SRC_IC5 + 1)

STM32_SRC_IC7

#define STM32_SRC_IC7   (STM32_SRC_IC6 + 1)

STM32_SRC_IC8

#define STM32_SRC_IC8   (STM32_SRC_IC7 + 1)

STM32_SRC_IC9

#define STM32_SRC_IC9   (STM32_SRC_IC8 + 1)

STM32_SRC_MSI

#define STM32_SRC_MSI   (STM32_SRC_HSI + 1)

STM32_SRC_PLL1

#define STM32_SRC_PLL1   (STM32_SRC_MSI + 1)

PLL outputs.

STM32_SRC_PLL2

#define STM32_SRC_PLL2   (STM32_SRC_PLL1 + 1)

STM32_SRC_PLL3

#define STM32_SRC_PLL3   (STM32_SRC_PLL2 + 1)

STM32_SRC_PLL4

#define STM32_SRC_PLL4   (STM32_SRC_PLL3 + 1)

UART4_SEL

#define UART4_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 12, CCIPR13_REG)

UART5_SEL

#define UART5_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 16, CCIPR13_REG)

UART7_SEL

#define UART7_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 24, CCIPR13_REG)

UART8_SEL

#define UART8_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 28, CCIPR13_REG)

UART9_SEL

#define UART9_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR14_REG)

CCIPR14 devices.

USART10_SEL

#define USART10_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR14_REG)

USART1_SEL

#define USART1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 0, CCIPR13_REG)

CCIPR13 devices.

USART2_SEL

#define USART2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 4, CCIPR13_REG)

USART3_SEL

#define USART3_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 8, CCIPR13_REG)

USART6_SEL

#define USART6_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 7, 20, CCIPR13_REG)

XSPI1_SEL

#define XSPI1_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 0, CCIPR6_REG)

CCIPR6 devices.

XSPI2_SEL

#define XSPI2_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 4, CCIPR6_REG)

XSPI3_SEL

#define XSPI3_SEL

(

val

)

STM32_DOMAIN_CLOCK((val), 3, 8, CCIPR6_REG)