Zephyr Project API
4.2.99
A Scalable Open Source RTOS
Loading...
Searching...
No Matches
stm32u3_clock.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2025 STMicroelectronics
3
*
4
* SPDX-License-Identifier: Apache-2.0
5
*/
6
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_
7
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_
8
9
#include "
stm32_common_clocks.h
"
10
13
/* RM0487, Figure 36 Clock tree for STM32U3 Series */
14
16
/* defined in stm32_common_clocks.h */
18
#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
19
#define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)
20
#define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1)
21
#define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1)
22
#define STM32_SRC_MSIK (STM32_SRC_MSIS + 1)
24
#define STM32_SRC_HCLK (STM32_SRC_MSIK + 1)
25
#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1)
26
#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)
27
#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1)
29
/* #define STM32_SRC_ICLK TBD */
30
32
#define STM32_CLOCK_BUS_AHB1 0x088
33
#define STM32_CLOCK_BUS_AHB1_2 0x094
34
#define STM32_CLOCK_BUS_AHB2 0x08C
35
#define STM32_CLOCK_BUS_AHB2_2 0x090
36
#define STM32_CLOCK_BUS_APB1 0x09C
37
#define STM32_CLOCK_BUS_APB1_2 0x0A0
38
#define STM32_CLOCK_BUS_APB2 0x0A4
39
#define STM32_CLOCK_BUS_APB3 0x0A8
40
41
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
42
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3
43
45
#define CCIPR1_REG 0x100
46
#define CCIPR2_REG 0x104
47
#define CCIPR3_REG 0x108
48
50
#define BDCR_REG 0x110
51
53
#define CFGR1_REG 0x0C
54
57
#define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0, 0, CCIPR1_REG)
58
#define USART3_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 2, CCIPR1_REG)
59
#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 4, 4, CCIPR1_REG)
60
#define UART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR1_REG)
61
#define I3C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 8, CCIPR1_REG)
62
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 10, CCIPR1_REG)
63
#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 12, 12, CCIPR1_REG)
64
#define I3C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR1_REG)
65
#define SPI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, CCIPR1_REG)
66
#define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR1_REG)
67
#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR1_REG)
68
#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR1_REG)
69
#define FDCAN1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR1_REG)
70
#define ICLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR1_REG)
71
#define USB1_SEL(val) STM32_DT_CLOCK_SELECT((val), 28, 28, CCIPR1_REG)
72
#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 29, CCIPR1_REG)
74
#define ADF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG)
75
#define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG)
76
#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 5, CCIPR2_REG)
77
#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 11, CCIPR2_REG)
78
#define ADCDAC_PRE(val) STM32_DT_CLOCK_SELECT((val), 15, 12, CCIPR2_REG)
79
#define ADCDAC_SEL(val) STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR2_REG)
80
#define DAC1SH_SEL(val) STM32_DT_CLOCK_SELECT((val), 19, 19, CCIPR2_REG)
81
#define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR2_REG)
83
#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR3_REG)
84
#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR3_REG)
85
#define LPTIM34_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR3_REG)
86
#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR3_REG)
88
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)
89
91
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG)
92
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR1_REG)
93
94
/* MCO prescaler : division factor */
95
#define MCO_PRE_DIV_1 0
96
#define MCO_PRE_DIV_2 1
97
#define MCO_PRE_DIV_4 2
98
#define MCO_PRE_DIV_8 3
99
#define MCO_PRE_DIV_16 4
100
#define MCO_PRE_DIV_32 5
101
#define MCO_PRE_DIV_64 6
102
#define MCO_PRE_DIV_128 7
103
104
/* ADC/DAC prescaler division factor */
105
#define ADCDAC_PRE_DIV_1 0x0
106
#define ADCDAC_PRE_DIV_2 0x1
107
#define ADCDAC_PRE_DIV_4 0x8
108
#define ADCDAC_PRE_DIV_8 0x9
109
#define ADCDAC_PRE_DIV_16 0xA
110
#define ADCDAC_PRE_DIV_32 0xB
111
#define ADCDAC_PRE_DIV_64 0xC
112
#define ADCDAC_PRE_DIV_128 0xD
113
#define ADCDAC_PRE_DIV_256 0xE
114
#define ADCDAC_PRE_DIV_512 0xF
115
116
#endif
/* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U3_CLOCK_H_ */
stm32_common_clocks.h
include
zephyr
dt-bindings
clock
stm32u3_clock.h
Generated on Sat Oct 25 2025 09:08:48 for Zephyr Project API by
1.9.8
1.9.8