stm32u3_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_SRC_HSE   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_HSI16   (STM32_SRC_HSE + 1)
#define	STM32_SRC_HSI48   (STM32_SRC_HSI16 + 1)
#define	STM32_SRC_MSIS   (STM32_SRC_HSI48 + 1)
#define	STM32_SRC_MSIK   (STM32_SRC_MSIS + 1)
#define	STM32_SRC_HCLK   (STM32_SRC_MSIK + 1)
	Bus clock.
#define	STM32_SRC_PCLK1   (STM32_SRC_HCLK + 1)
#define	STM32_SRC_PCLK2   (STM32_SRC_PCLK1 + 1)
#define	STM32_SRC_PCLK3   (STM32_SRC_PCLK2 + 1)
#define	STM32_CLOCK_BUS_AHB1   0x088
	Clock muxes.
#define	STM32_CLOCK_BUS_AHB1_2   0x094
#define	STM32_CLOCK_BUS_AHB2   0x08C
#define	STM32_CLOCK_BUS_AHB2_2   0x090
#define	STM32_CLOCK_BUS_APB1   0x09C
#define	STM32_CLOCK_BUS_APB1_2   0x0A0
#define	STM32_CLOCK_BUS_APB2   0x0A4
#define	STM32_CLOCK_BUS_APB3   0x0A8
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3
#define	CCIPR1_REG   0x100
	RCC_CCIPRx register offset (RM0487.pdf)
#define	CCIPR2_REG   0x104
#define	CCIPR3_REG   0x108
#define	BDCR_REG   0x110
	RCC_BDCR register offset.
#define	CFGR1_REG   0x0C
	RCC_CFGRx register offset.
#define	USART1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 0, 0, CCIPR1_REG)
	Device domain clocks selection helpers.
#define	USART3_SEL(val)   STM32_DT_CLOCK_SELECT((val), 2, 2, CCIPR1_REG)
#define	UART4_SEL(val)   STM32_DT_CLOCK_SELECT((val), 4, 4, CCIPR1_REG)
#define	UART5_SEL(val)   STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR1_REG)
#define	I3C1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 8, 8, CCIPR1_REG)
#define	I2C1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 10, 10, CCIPR1_REG)
#define	I2C2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 12, 12, CCIPR1_REG)
#define	I3C2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR1_REG)
#define	SPI2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 16, 16, CCIPR1_REG)
#define	LPTIM2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR1_REG)
#define	SPI1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR1_REG)
#define	SYSTICK_SEL(val)   STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR1_REG)
#define	FDCAN1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR1_REG)
#define	ICLK_SEL(val)   STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR1_REG)
#define	USB1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 28, 28, CCIPR1_REG)
#define	TIMIC_SEL(val)   STM32_DT_CLOCK_SELECT((val), 31, 29, CCIPR1_REG)
#define	ADF1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG)
	CCIPR2 devices.
#define	SPI3_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG)
#define	SAI1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 6, 5, CCIPR2_REG)
#define	RNG_SEL(val)   STM32_DT_CLOCK_SELECT((val), 11, 11, CCIPR2_REG)
#define	ADCDAC_PRE(val)   STM32_DT_CLOCK_SELECT((val), 15, 12, CCIPR2_REG)
#define	ADCDAC_SEL(val)   STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR2_REG)
#define	DAC1SH_SEL(val)   STM32_DT_CLOCK_SELECT((val), 19, 19, CCIPR2_REG)
#define	OCTOSPI_SEL(val)   STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR2_REG)
#define	LPUART1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR3_REG)
	CCIPR3 devices.
#define	I2C3_SEL(val)   STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR3_REG)
#define	LPTIM34_SEL(val)   STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR3_REG)
#define	LPTIM1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR3_REG)
#define	RTC_SEL(val)   STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)
	BDCR devices.
#define	MCO1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG)
	CFGR1 devices.
#define	MCO1_PRE(val)   STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR1_REG)
#define	MCO_PRE_DIV_1   0
#define	MCO_PRE_DIV_2   1
#define	MCO_PRE_DIV_4   2
#define	MCO_PRE_DIV_8   3
#define	MCO_PRE_DIV_16   4
#define	MCO_PRE_DIV_32   5
#define	MCO_PRE_DIV_64   6
#define	MCO_PRE_DIV_128   7
#define	ADCDAC_PRE_DIV_1   0x0
#define	ADCDAC_PRE_DIV_2   0x1
#define	ADCDAC_PRE_DIV_4   0x8
#define	ADCDAC_PRE_DIV_8   0x9
#define	ADCDAC_PRE_DIV_16   0xA
#define	ADCDAC_PRE_DIV_32   0xB
#define	ADCDAC_PRE_DIV_64   0xC
#define	ADCDAC_PRE_DIV_128   0xD
#define	ADCDAC_PRE_DIV_256   0xE
#define	ADCDAC_PRE_DIV_512   0xF

Macro Definition Documentation

ADCDAC_PRE

#define ADCDAC_PRE

(

val

)

STM32_DT_CLOCK_SELECT((val), 15, 12, CCIPR2_REG)

ADCDAC_PRE_DIV_1

#define ADCDAC_PRE_DIV_1   0x0

ADCDAC_PRE_DIV_128

#define ADCDAC_PRE_DIV_128   0xD

ADCDAC_PRE_DIV_16

#define ADCDAC_PRE_DIV_16   0xA

ADCDAC_PRE_DIV_2

#define ADCDAC_PRE_DIV_2   0x1

ADCDAC_PRE_DIV_256

#define ADCDAC_PRE_DIV_256   0xE

ADCDAC_PRE_DIV_32

#define ADCDAC_PRE_DIV_32   0xB

ADCDAC_PRE_DIV_4

#define ADCDAC_PRE_DIV_4   0x8

ADCDAC_PRE_DIV_512

#define ADCDAC_PRE_DIV_512   0xF

ADCDAC_PRE_DIV_64

#define ADCDAC_PRE_DIV_64   0xC

ADCDAC_PRE_DIV_8

#define ADCDAC_PRE_DIV_8   0x9

ADCDAC_SEL

#define ADCDAC_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 17, 16, CCIPR2_REG)

ADF1_SEL

#define ADF1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR2_REG)

CCIPR2 devices.

BDCR_REG

#define BDCR_REG   0x110

RCC_BDCR register offset.

CCIPR1_REG

#define CCIPR1_REG   0x100

RCC_CCIPRx register offset (RM0487.pdf)

CCIPR2_REG

#define CCIPR2_REG   0x104

CCIPR3_REG

#define CCIPR3_REG   0x108

CFGR1_REG

#define CFGR1_REG   0x0C

RCC_CFGRx register offset.

DAC1SH_SEL

#define DAC1SH_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 19, 19, CCIPR2_REG)

FDCAN1_SEL

#define FDCAN1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR1_REG)

I2C1_SEL

#define I2C1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 10, 10, CCIPR1_REG)

I2C2_SEL

#define I2C2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 12, 12, CCIPR1_REG)

I2C3_SEL

#define I2C3_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR3_REG)

I3C1_SEL

#define I3C1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 8, 8, CCIPR1_REG)

I3C2_SEL

#define I3C2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR1_REG)

ICLK_SEL

#define ICLK_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 27, 26, CCIPR1_REG)

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR3_REG)

LPTIM2_SEL

#define LPTIM2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 19, 18, CCIPR1_REG)

LPTIM34_SEL

#define LPTIM34_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR3_REG)

LPUART1_SEL

#define LPUART1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 1, 0, CCIPR3_REG)

CCIPR3 devices.

MCO1_PRE

#define MCO1_PRE

(

val

)

STM32_DT_CLOCK_SELECT((val), 30, 28, CFGR1_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 27, 24, CFGR1_REG)

CFGR1 devices.

MCO_PRE_DIV_1

#define MCO_PRE_DIV_1   0

MCO_PRE_DIV_128

#define MCO_PRE_DIV_128   7

MCO_PRE_DIV_16

#define MCO_PRE_DIV_16   4

MCO_PRE_DIV_2

#define MCO_PRE_DIV_2   1

MCO_PRE_DIV_32

#define MCO_PRE_DIV_32   5

MCO_PRE_DIV_4

#define MCO_PRE_DIV_4   2

MCO_PRE_DIV_64

#define MCO_PRE_DIV_64   6

MCO_PRE_DIV_8

#define MCO_PRE_DIV_8   3

OCTOSPI_SEL

#define OCTOSPI_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR2_REG)

RNG_SEL

#define RNG_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 11, 11, CCIPR2_REG)

RTC_SEL

#define RTC_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)

BDCR devices.

SAI1_SEL

#define SAI1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 6, 5, CCIPR2_REG)

SPI1_SEL

#define SPI1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 20, 20, CCIPR1_REG)

SPI2_SEL

#define SPI2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 16, 16, CCIPR1_REG)

SPI3_SEL

#define SPI3_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG)

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x088

Clock muxes.

Bus clocks

STM32_CLOCK_BUS_AHB1_2

#define STM32_CLOCK_BUS_AHB1_2   0x094

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x08C

STM32_CLOCK_BUS_AHB2_2

#define STM32_CLOCK_BUS_AHB2_2   0x090

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x09C

STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x0A0

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x0A4

STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x0A8

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_HCLK

#define STM32_SRC_HCLK   (STM32_SRC_MSIK + 1)

Bus clock.

STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_HSI16

#define STM32_SRC_HSI16   (STM32_SRC_HSE + 1)

STM32_SRC_HSI48

#define STM32_SRC_HSI48   (STM32_SRC_HSI16 + 1)

STM32_SRC_MSIK

#define STM32_SRC_MSIK   (STM32_SRC_MSIS + 1)

STM32_SRC_MSIS

#define STM32_SRC_MSIS   (STM32_SRC_HSI48 + 1)

STM32_SRC_PCLK1

#define STM32_SRC_PCLK1   (STM32_SRC_HCLK + 1)

STM32_SRC_PCLK2

#define STM32_SRC_PCLK2   (STM32_SRC_PCLK1 + 1)

STM32_SRC_PCLK3

#define STM32_SRC_PCLK3   (STM32_SRC_PCLK2 + 1)

SYSTICK_SEL

#define SYSTICK_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR1_REG)

TIMIC_SEL

#define TIMIC_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 31, 29, CCIPR1_REG)

UART4_SEL

#define UART4_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 4, 4, CCIPR1_REG)

UART5_SEL

#define UART5_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 6, 6, CCIPR1_REG)

USART1_SEL

#define USART1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 0, 0, CCIPR1_REG)

Device domain clocks selection helpers.

CCIPR1 devices

USART3_SEL

#define USART3_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 2, 2, CCIPR1_REG)

USB1_SEL

#define USB1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 28, 28, CCIPR1_REG)