stm32wb0_clock.h

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/*
 * Copyright (c) 2024 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
 
#include <zephyr/dt-bindings/clock/stm32_common_clocks.h>


#define STM32_SRC_CLKSLOWMUX            (STM32_SRC_LSI + 1)
#define STM32_SRC_CLK16MHZ              (STM32_SRC_CLKSLOWMUX + 1)
#define STM32_SRC_CLK32MHZ              (STM32_SRC_CLK16MHZ + 1)

#define STM32_CLOCK_BUS_AHB0    0x50
#define STM32_CLOCK_BUS_APB0    0x54
#define STM32_CLOCK_BUS_APB1    0x58
#define STM32_CLOCK_BUS_APB2    0x60
 
#define STM32_PERIPH_BUS_MIN    STM32_CLOCK_BUS_AHB0
#define STM32_PERIPH_BUS_MAX    STM32_CLOCK_BUS_APB2

#define CFGR_REG        0x08

#define APB2ENR_REG     0x60

 
/* WB05/WB09 only */
#define LPUART1_SEL(val)        STM32_DT_CLOCK_SELECT((val), 13, 13, CFGR_REG)
/* WB06/WB07 only */
#define SPI2_I2S2_SEL(val)      STM32_DT_CLOCK_SELECT((val), 22, 22, CFGR_REG)
/* `msb` is only 22 for WB06/WB07, but a single definition with msb=23 is acceptable */
#define SPI3_I2S3_SEL(val)      STM32_DT_CLOCK_SELECT((val), 23, 22, CFGR_REG)

 
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ */