| Zephyr Project API 4.2.99
    A Scalable Open Source RTOS | 
#include "stm32_common_clocks.h"Go to the source code of this file.
| Macros | |
| #define | STM32_SRC_CLKSLOWMUX (STM32_SRC_LSI + 1) | 
| Define system & low-speed clocks. | |
| #define | STM32_SRC_CLK16MHZ (STM32_SRC_CLKSLOWMUX + 1) | 
| #define | STM32_SRC_CLK32MHZ (STM32_SRC_CLK16MHZ + 1) | 
| #define | STM32_CLOCK_BUS_AHB0 0x50 | 
| Bus clocks. | |
| #define | STM32_CLOCK_BUS_APB0 0x54 | 
| #define | STM32_CLOCK_BUS_APB1 0x58 | 
| #define | STM32_CLOCK_BUS_APB2 0x60 | 
| #define | STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB0 | 
| #define | STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2 | 
| #define | CFGR_REG 0x08 | 
| RCC_CFGR register offset. | |
| #define | APB2ENR_REG 0x60 | 
| RCC_APB2ENR register offset. | |
| #define | LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 13, CFGR_REG) | 
| Device clk sources selection helpers. | |
| #define | SPI2_I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 22, 22, CFGR_REG) | 
| #define | SPI3_I2S3_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CFGR_REG) | 
| #define APB2ENR_REG 0x60 | 
RCC_APB2ENR register offset.
| #define CFGR_REG 0x08 | 
RCC_CFGR register offset.
| #define LPUART1_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 13, 13, CFGR_REG) | 
Device clk sources selection helpers.
| #define SPI2_I2S2_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 22, 22, CFGR_REG) | 
| #define SPI3_I2S3_SEL | ( | val | ) | STM32_DT_CLOCK_SELECT((val), 23, 22, CFGR_REG) | 
| #define STM32_CLOCK_BUS_AHB0 0x50 | 
Bus clocks.
| #define STM32_CLOCK_BUS_APB0 0x54 | 
| #define STM32_CLOCK_BUS_APB1 0x58 | 
| #define STM32_CLOCK_BUS_APB2 0x60 | 
| #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2 | 
| #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB0 | 
| #define STM32_SRC_CLK16MHZ (STM32_SRC_CLKSLOWMUX + 1) | 
| #define STM32_SRC_CLK32MHZ (STM32_SRC_CLK16MHZ + 1) | 
| #define STM32_SRC_CLKSLOWMUX (STM32_SRC_LSI + 1) | 
Define system & low-speed clocks.
Other fixed clocks.