stm32wb0_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_SRC_CLKSLOWMUX   (STM32_SRC_LSI + 1)
	Define system & low-speed clocks.
#define	STM32_SRC_CLK16MHZ   (STM32_SRC_CLKSLOWMUX + 1)
#define	STM32_SRC_CLK32MHZ   (STM32_SRC_CLK16MHZ + 1)
#define	STM32_CLOCK_BUS_AHB0   0x50
	Bus clocks.
#define	STM32_CLOCK_BUS_APB0   0x54
#define	STM32_CLOCK_BUS_APB1   0x58
#define	STM32_CLOCK_BUS_APB2   0x60
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB0
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB2
#define	STM32_CLOCK_REG_MASK   (0xFFFFU)
#define	STM32_CLOCK_REG_SHIFT   (0U)
#define	STM32_CLOCK_SHIFT_MASK   (0x3FU)
#define	STM32_CLOCK_SHIFT_SHIFT   (16U)
#define	STM32_CLOCK_MASK_MASK   (0x1FU)
#define	STM32_CLOCK_MASK_SHIFT   (22U)
#define	STM32_CLOCK_VAL_MASK   STM32_CLOCK_MASK_MASK
#define	STM32_CLOCK_VAL_SHIFT   (27U)
#define	STM32_DOMAIN_CLOCK(val, mask, shift, reg)
	STM32 clock configuration bit field.
#define	CFGR_REG   0x08
	RCC_CFGR register offset.
#define	APB2ENR_REG   0x60
	RCC_APB2ENR register offset.
#define	LPUART1_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 13, CFGR_REG) /* WB05/WB09 only */
	Device clk sources selection helpers.
#define	SPI2_I2S2_SEL(val)   STM32_DOMAIN_CLOCK(val, 1, 22, CFGR_REG) /* WB06/WB07 only */
#define	SPI3_I2S3_SEL(val)   STM32_DOMAIN_CLOCK(val, 3, 22, CFGR_REG)

Macro Definition Documentation

APB2ENR_REG

#define APB2ENR_REG   0x60

RCC_APB2ENR register offset.

CFGR_REG

#define CFGR_REG   0x08

RCC_CFGR register offset.

LPUART1_SEL

#define LPUART1_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 13, CFGR_REG) /* WB05/WB09 only */

Device clk sources selection helpers.

SPI2_I2S2_SEL

#define SPI2_I2S2_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 1, 22, CFGR_REG) /* WB06/WB07 only */

SPI3_I2S3_SEL

#define SPI3_I2S3_SEL

(

val

)

STM32_DOMAIN_CLOCK(val, 3, 22, CFGR_REG)

STM32_CLOCK_BUS_AHB0

#define STM32_CLOCK_BUS_AHB0   0x50

Bus clocks.

STM32_CLOCK_BUS_APB0

#define STM32_CLOCK_BUS_APB0   0x54

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x58

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x60

STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK   (0x1FU)

STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT   (22U)

STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK   (0xFFFFU)

STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT   (0U)

STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK   (0x3FU)

STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT   (16U)

STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK   STM32_CLOCK_MASK_MASK

STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT   (27U)

STM32_DOMAIN_CLOCK

#define STM32_DOMAIN_CLOCK	(		val,
			mask,
			shift,
			reg
	)

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32 clock configuration bit field.

Parameters

reg	Offset to target configuration register in RCC
shift	Position of field within RCC register (= field LSB's index)
mask	Mask of field in RCC register
val	Field value

Note

'reg' range: 0x0~0xFFFF [ 00 : 15 ]

'shift' range: 0~63 [ 16 : 21 ]

'mask' range: 0x00~0x1F [ 22 : 26 ]

'val' range: 0x00~0x1F [ 27 : 31 ]

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB2

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB0

STM32_SRC_CLK16MHZ

#define STM32_SRC_CLK16MHZ   (STM32_SRC_CLKSLOWMUX + 1)

STM32_SRC_CLK32MHZ

#define STM32_SRC_CLK32MHZ   (STM32_SRC_CLK16MHZ + 1)

STM32_SRC_CLKSLOWMUX

#define STM32_SRC_CLKSLOWMUX   (STM32_SRC_LSI + 1)

Define system & low-speed clocks.

Other fixed clocks.

• CLKSLOWMUX: used to query slow clock tree frequency
• CLK16MHZ: secondary clock for LPUART, SPI3/I2S and BLE
• CLK32MHZ: secondary clock for SPI3/I2S and BLE