Zephyr Project API 4.1.0
A Scalable Open Source RTOS
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stm32u0_clock.h File Reference

Go to the source code of this file.

Macros

#define STM32_CLOCK_BUS_AHB1   0x48
 Bus gatting clocks.
 
#define STM32_CLOCK_BUS_IOP   0x4C
 
#define STM32_CLOCK_BUS_APB1   0x58
 
#define STM32_CLOCK_BUS_APB1_2   0x60
 
#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
 
#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1_2
 
#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)
 Domain clocks.
 
#define STM32_SRC_HSI48   (STM32_SRC_HSI + 1)
 
#define STM32_SRC_MSI   (STM32_SRC_HSI48 + 1)
 
#define STM32_SRC_HSE   (STM32_SRC_MSI + 1)
 
#define STM32_SRC_PCLK   (STM32_SRC_HSE + 1)
 Peripheral bus clock.
 
#define STM32_SRC_PLL_P   (STM32_SRC_PCLK + 1)
 PLL clock outputs.
 
#define STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)
 
#define STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)
 
#define CCIPR_REG   0x88
 RCC_CCIPR register offset.
 
#define BDCR_REG   0x90
 RCC_BDCR register offset.
 
#define USART1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
 Device domain clocks selection helpers.
 
#define USART2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
 
#define LPUART3_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG)
 
#define LPUART2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
 
#define LPUART1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
 
#define I2C1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
 
#define I2C3_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
 
#define LPTIM1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
 
#define LPTIM2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
 
#define LPTIM3_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
 
#define TIM1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG)
 
#define TIM15_SEL(val)   STM32_DT_CLOCK_SELECT((val), 1, 25, CCIPR_REG)
 
#define CLK48_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
 
#define ADC_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
 
#define RTC_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 BDCR devices.
 

Macro Definition Documentation

◆ ADC_SEL

#define ADC_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)

◆ BDCR_REG

#define BDCR_REG   0x90

RCC_BDCR register offset.

◆ CCIPR_REG

#define CCIPR_REG   0x88

RCC_CCIPR register offset.

◆ CLK48_SEL

#define CLK48_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)

◆ I2C1_SEL

#define I2C1_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)

◆ I2C3_SEL

#define I2C3_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)

◆ LPTIM1_SEL

#define LPTIM1_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)

◆ LPTIM2_SEL

#define LPTIM2_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)

◆ LPTIM3_SEL

#define LPTIM3_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)

◆ LPUART1_SEL

#define LPUART1_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)

◆ LPUART2_SEL

#define LPUART2_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)

◆ LPUART3_SEL

#define LPUART3_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG)

◆ RTC_SEL

#define RTC_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)

BDCR devices.

◆ STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x48

Bus gatting clocks.

◆ STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x58

◆ STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x60

◆ STM32_CLOCK_BUS_IOP

#define STM32_CLOCK_BUS_IOP   0x4C

◆ STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB1_2

◆ STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

◆ STM32_SRC_HSE

#define STM32_SRC_HSE   (STM32_SRC_MSI + 1)

◆ STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

◆ STM32_SRC_HSI48

#define STM32_SRC_HSI48   (STM32_SRC_HSI + 1)

◆ STM32_SRC_MSI

#define STM32_SRC_MSI   (STM32_SRC_HSI48 + 1)

◆ STM32_SRC_PCLK

#define STM32_SRC_PCLK   (STM32_SRC_HSE + 1)

Peripheral bus clock.

◆ STM32_SRC_PLL_P

#define STM32_SRC_PLL_P   (STM32_SRC_PCLK + 1)

PLL clock outputs.

◆ STM32_SRC_PLL_Q

#define STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)

◆ STM32_SRC_PLL_R

#define STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)

◆ TIM15_SEL

#define TIM15_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 1, 25, CCIPR_REG)

◆ TIM1_SEL

#define TIM1_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG)

◆ USART1_SEL

#define USART1_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)

Device domain clocks selection helpers.

CCIPR devices

◆ USART2_SEL

#define USART2_SEL (   val)    STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)