#include "stm32_common_clocks.h"

Macros
#define	STM32_CLOCK_BUS_AHB1 0x048
	Bus clocks.

#define	STM32_CLOCK_BUS_AHB2 0x04c

#define	STM32_CLOCK_BUS_AHB3 0x050

#define	STM32_CLOCK_BUS_APB1 0x058

#define	STM32_CLOCK_BUS_APB1_2 0x05c

#define	STM32_CLOCK_BUS_APB2 0x060

#define	STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1

#define	STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2

#define	STM32_SRC_HSI (STM32_SRC_LSI + 1)
	Domain clocks.

#define	STM32_SRC_HSI48 (STM32_SRC_HSI + 1)

#define	STM32_SRC_MSI (STM32_SRC_HSI48 + 1)

#define	STM32_SRC_HSE (STM32_SRC_MSI + 1)

#define	STM32_SRC_PCLK (STM32_SRC_HSE + 1)
	Bus clock.

#define	STM32_SRC_PLL_P (STM32_SRC_PCLK + 1)
	PLL clock outputs.

#define	STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)

#define	STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)

#define	STM32_CLOCK_REG_MASK 0xFFU

#define	STM32_CLOCK_REG_SHIFT 0U

#define	STM32_CLOCK_SHIFT_MASK 0x1FU

#define	STM32_CLOCK_SHIFT_SHIFT 8U

#define	STM32_CLOCK_MASK_MASK 0x7U

#define	STM32_CLOCK_MASK_SHIFT 13U

#define	STM32_CLOCK_VAL_MASK 0x7U

#define	STM32_CLOCK_VAL_SHIFT 16U

#define	STM32_DOMAIN_CLOCK(val, mask, shift, reg)
	STM32 clock configuration bit field.

#define	CCIPR_REG 0x88
	RCC_CCIPR register offset.

#define	BDCR_REG 0x90
	RCC_BDCR register offset.

#define	CSR_REG 0x94
	RCC_CSR register offset.

#define	USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
	Device domain clocks selection helpers.

#define	LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)

#define	I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)

#define	I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)

#define	LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)

#define	LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)

#define	SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)

#define	CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)

#define	ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)

#define	RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)

#define	RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
	BDCR devices.

#define	RFWKP_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CSR_REG)
	CSR devices.

Macro Definition Documentation

◆ ADC_SEL

#define ADC_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)

◆ BDCR_REG

#define BDCR_REG 0x90

RCC_BDCR register offset.

◆ CCIPR_REG

#define CCIPR_REG 0x88

RCC_CCIPR register offset.

◆ CLK48_SEL

#define CLK48_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)

◆ CSR_REG

#define CSR_REG 0x94

RCC_CSR register offset.

◆ I2C1_SEL

#define I2C1_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)

◆ I2C3_SEL

#define I2C3_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)

◆ LPTIM1_SEL

#define LPTIM1_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)

◆ LPTIM2_SEL

#define LPTIM2_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)

◆ LPUART1_SEL

#define LPUART1_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)

◆ RFWKP_SEL

#define RFWKP_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 14, CSR_REG)

CSR devices.

◆ RNG_SEL

#define RNG_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)

◆ RTC_SEL

#define RTC_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)

BDCR devices.

◆ SAI1_SEL

#define SAI1_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)

◆ STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1 0x048

Bus clocks.

◆ STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2 0x04c

◆ STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3 0x050

◆ STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1 0x058

◆ STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2 0x05c

◆ STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2 0x060

◆ STM32_CLOCK_MASK_MASK

#define STM32_CLOCK_MASK_MASK 0x7U

◆ STM32_CLOCK_MASK_SHIFT

#define STM32_CLOCK_MASK_SHIFT 13U

◆ STM32_CLOCK_REG_MASK

#define STM32_CLOCK_REG_MASK 0xFFU

◆ STM32_CLOCK_REG_SHIFT

#define STM32_CLOCK_REG_SHIFT 0U

◆ STM32_CLOCK_SHIFT_MASK

#define STM32_CLOCK_SHIFT_MASK 0x1FU

◆ STM32_CLOCK_SHIFT_SHIFT

#define STM32_CLOCK_SHIFT_SHIFT 8U

◆ STM32_CLOCK_VAL_MASK

#define STM32_CLOCK_VAL_MASK 0x7U

◆ STM32_CLOCK_VAL_SHIFT

#define STM32_CLOCK_VAL_SHIFT 16U

◆ STM32_DOMAIN_CLOCK

#define STM32_DOMAIN_CLOCK	(	val,
		mask,
		shift,
		reg
	)

Value:

        ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |            \
         (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |      \
         (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |         \
         (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))

STM32 clock configuration bit field.

reg (1/2/3) [ 0 : 7 ]
shift (0..31) [ 8 : 12 ]
mask (0x1, 0x3, 0x7) [ 13 : 15 ]
val (0..7) [ 16 : 18 ]

Parameters

reg	RCC_CCIPRx register offset
shift	Position within RCC_CCIPRx.
mask	Mask for the RCC_CCIPRx field.
val	Clock value (0, 1, ... 7).

◆ STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2

◆ STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1

◆ STM32_SRC_HSE

#define STM32_SRC_HSE (STM32_SRC_MSI + 1)

◆ STM32_SRC_HSI

#define STM32_SRC_HSI (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

◆ STM32_SRC_HSI48

#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1)

◆ STM32_SRC_MSI

#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)

◆ STM32_SRC_PCLK

#define STM32_SRC_PCLK (STM32_SRC_HSE + 1)

Bus clock.

◆ STM32_SRC_PLL_P

#define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1)

PLL clock outputs.

◆ STM32_SRC_PLL_Q

#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1)

◆ STM32_SRC_PLL_R

#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1)

◆ USART1_SEL

#define USART1_SEL ( val ) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)

Device domain clocks selection helpers.

CCIPR devices

Macros