stm32wl_clock.h File Reference

#include "stm32_common_clocks.h"

Go to the source code of this file.

Macros
#define	STM32_CLOCK_BUS_AHB1   0x048
	Bus clocks.
#define	STM32_CLOCK_BUS_AHB2   0x04c
#define	STM32_CLOCK_BUS_AHB3   0x050
#define	STM32_CLOCK_BUS_APB1   0x058
#define	STM32_CLOCK_BUS_APB1_2   0x05c
#define	STM32_CLOCK_BUS_APB2   0x060
#define	STM32_CLOCK_BUS_APB3   0x064
#define	STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1
#define	STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3
#define	STM32_SRC_HSI   (STM32_SRC_LSI + 1)
	Domain clocks.
#define	STM32_SRC_MSI   (STM32_SRC_HSI + 1)
#define	STM32_SRC_PCLK   (STM32_SRC_MSI + 1)
	Bus clock.
#define	STM32_SRC_PLL_P   (STM32_SRC_PCLK + 1)
	PLL clock outputs.
#define	STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)
#define	STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)
#define	CCIPR_REG   0x88
	RCC_CCIPR register offset.
#define	BDCR_REG   0x90
	RCC_BDCR register offset.
#define	CFGR1_REG   0x08
	RCC_CFGRx register offset.
#define	USART1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
	Device domain clocks selection helpers.
#define	USART2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
#define	SPI2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
#define	LPUART1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
#define	I2C1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
#define	I2C2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
#define	I2C3_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
#define	LPTIM1_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
#define	LPTIM2_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
#define	LPTIM3_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
#define	ADC_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
#define	RNG_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
#define	RTC_SEL(val)   STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
	BDCR devices.
#define	MCO1_SEL(val)   STM32_DT_CLOCK_SELECT(val, 0xF, 24, CFGR1_REG)
	CFGR1 devices.
#define	MCO1_PRE(val)   STM32_DT_CLOCK_SELECT(val, 0x7, 28, CFGR1_REG)
#define	MCO_PRE_DIV_1   0
#define	MCO_PRE_DIV_2   1
#define	MCO_PRE_DIV_4   2
#define	MCO_PRE_DIV_8   3
#define	MCO_PRE_DIV_16   4
#define	MCO_SEL_NOCLK   0
#define	MCO_SEL_SYSCLKPRE   1
#define	MCO_SEL_MSI   2
#define	MCO_SEL_HSI16   3
#define	MCO_SEL_HSE32   4
#define	MCO_SEL_PLL1RCLK   5
#define	MCO_SEL_LSI   6
#define	MCO_SEL_LSE   8
#define	MCO_SEL_PLL1PCLK   13
#define	MCO_SEL_PLL1QCLK   14

Macro Definition Documentation

ADC_SEL

#define ADC_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)

BDCR_REG

#define BDCR_REG   0x90

RCC_BDCR register offset.

CCIPR_REG

#define CCIPR_REG   0x88

RCC_CCIPR register offset.

CFGR1_REG

#define CFGR1_REG   0x08

RCC_CFGRx register offset.

I2C1_SEL

#define I2C1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)

I2C2_SEL

#define I2C2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)

I2C3_SEL

#define I2C3_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)

LPTIM1_SEL

#define LPTIM1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)

LPTIM2_SEL

#define LPTIM2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)

LPTIM3_SEL

#define LPTIM3_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)

LPUART1_SEL

#define LPUART1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)

MCO1_PRE

#define MCO1_PRE

(

val

)

STM32_DT_CLOCK_SELECT(val, 0x7, 28, CFGR1_REG)

MCO1_SEL

#define MCO1_SEL

(

val

)

STM32_DT_CLOCK_SELECT(val, 0xF, 24, CFGR1_REG)

CFGR1 devices.

MCO_PRE_DIV_1

#define MCO_PRE_DIV_1   0

MCO_PRE_DIV_16

#define MCO_PRE_DIV_16   4

MCO_PRE_DIV_2

#define MCO_PRE_DIV_2   1

MCO_PRE_DIV_4

#define MCO_PRE_DIV_4   2

MCO_PRE_DIV_8

#define MCO_PRE_DIV_8   3

MCO_SEL_HSE32

#define MCO_SEL_HSE32   4

MCO_SEL_HSI16

#define MCO_SEL_HSI16   3

MCO_SEL_LSE

#define MCO_SEL_LSE   8

MCO_SEL_LSI

#define MCO_SEL_LSI   6

MCO_SEL_MSI

#define MCO_SEL_MSI   2

MCO_SEL_NOCLK

#define MCO_SEL_NOCLK   0

MCO_SEL_PLL1PCLK

#define MCO_SEL_PLL1PCLK   13

MCO_SEL_PLL1QCLK

#define MCO_SEL_PLL1QCLK   14

MCO_SEL_PLL1RCLK

#define MCO_SEL_PLL1RCLK   5

MCO_SEL_SYSCLKPRE

#define MCO_SEL_SYSCLKPRE   1

RNG_SEL

#define RNG_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)

RTC_SEL

#define RTC_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)

BDCR devices.

SPI2_SEL

#define SPI2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)

STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1   0x048

Bus clocks.

STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2   0x04c

STM32_CLOCK_BUS_AHB3

#define STM32_CLOCK_BUS_AHB3   0x050

STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1   0x058

STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2   0x05c

STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2   0x060

STM32_CLOCK_BUS_APB3

#define STM32_CLOCK_BUS_APB3   0x064

STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX   STM32_CLOCK_BUS_APB3

STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN   STM32_CLOCK_BUS_AHB1

STM32_SRC_HSI

#define STM32_SRC_HSI   (STM32_SRC_LSI + 1)

Domain clocks.

System clock Fixed clocks

STM32_SRC_MSI

#define STM32_SRC_MSI   (STM32_SRC_HSI + 1)

STM32_SRC_PCLK

#define STM32_SRC_PCLK   (STM32_SRC_MSI + 1)

Bus clock.

STM32_SRC_PLL_P

#define STM32_SRC_PLL_P   (STM32_SRC_PCLK + 1)

PLL clock outputs.

STM32_SRC_PLL_Q

#define STM32_SRC_PLL_Q   (STM32_SRC_PLL_P + 1)

STM32_SRC_PLL_R

#define STM32_SRC_PLL_R   (STM32_SRC_PLL_Q + 1)

USART1_SEL

#define USART1_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)

Device domain clocks selection helpers.

CCIPR devices

USART2_SEL

#define USART2_SEL

(

val

)

STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)