#include "stm32_common_clocks.h"

Macros
#define	STM32_SRC_HSE (STM32_SRC_LSI + 1)
	Peripheral clock sources.

#define	STM32_SRC_HSI16 (STM32_SRC_HSE + 1)

#define	STM32_SRC_HCLK1 (STM32_SRC_HSI16 + 1)
	Bus clock.

#define	STM32_SRC_HCLK5 (STM32_SRC_HCLK1 + 1)

#define	STM32_SRC_PCLK1 (STM32_SRC_HCLK5 + 1)

#define	STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)

#define	STM32_SRC_PCLK7 (STM32_SRC_PCLK2 + 1)

#define	STM32_SRC_PLL1_P (STM32_SRC_PCLK7 + 1)
	PLL outputs.

#define	STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)

#define	STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)

#define	STM32_SRC_CLOCK_MIN STM32_SRC_PLL1_P

#define	STM32_SRC_CLOCK_MAX STM32_SRC_SYSCLK

#define	STM32_CLOCK_BUS_AHB1 0x088
	Bus clocks (Register address offsets)

#define	STM32_CLOCK_BUS_AHB2 0x08C

#define	STM32_CLOCK_BUS_AHB4 0x094

#define	STM32_CLOCK_BUS_AHB5 0x098

#define	STM32_CLOCK_BUS_APB1 0x09C

#define	STM32_CLOCK_BUS_APB1_2 0x0A0

#define	STM32_CLOCK_BUS_APB2 0x0A4

#define	STM32_CLOCK_BUS_APB7 0x0A8

#define	STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1

#define	STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB7

#define	CCIPR1_REG 0xE0
	RCC_CCIPRx register offset (RM0493.pdf)

#define	CCIPR2_REG 0xE4

#define	CCIPR3_REG 0xE8

#define	BCDR1_REG 0xF0
	RCC_BCDR1 register offset (RM0493.pdf)

#define	USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG)
	Device clk sources selection helpers.

#define	USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG)

#define	I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG)

#define	LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG)

#define	SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)

#define	SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)

#define	TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG)

#define	RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
	CCIPR2 devices.

#define	LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
	CCIPR3 devices.

#define	SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG)

#define	I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG)

#define	LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG)

#define	ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG)

#define	RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BCDR1_REG)
	BCDR1 devices.

#define	CFGR1_REG 0x1C
	RCC_CFGRx register offset.

#define	MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
	CFGR1 devices.

#define	MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)

#define	MCO_PRE_DIV_1 0

#define	MCO_PRE_DIV_2 1

#define	MCO_PRE_DIV_4 2

#define	MCO_PRE_DIV_8 3

#define	MCO_PRE_DIV_16 4

#define	MCO_SEL_SYSCLKPRE 1

#define	MCO_SEL_HSI16 3

#define	MCO_SEL_HSE32 4

#define	MCO_SEL_PLL1RCLK 5

#define	MCO_SEL_LSI 6

#define	MCO_SEL_LSE 7

#define	MCO_SEL_PLL1PCLK 8

#define	MCO_SEL_PLL1QCLK 9

#define	MCO_SEL_HCLK5 10

Macro Definition Documentation

◆ ADC_SEL

#define ADC_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG)

◆ BCDR1_REG

#define BCDR1_REG 0xF0

RCC_BCDR1 register offset (RM0493.pdf)

◆ CCIPR1_REG

#define CCIPR1_REG 0xE0

RCC_CCIPRx register offset (RM0493.pdf)

◆ CCIPR2_REG

#define CCIPR2_REG 0xE4

◆ CCIPR3_REG

#define CCIPR3_REG 0xE8

◆ CFGR1_REG

#define CFGR1_REG 0x1C

RCC_CFGRx register offset.

◆ I2C1_SEL

#define I2C1_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG)

◆ I2C3_SEL

#define I2C3_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG)

◆ LPTIM1_SEL

#define LPTIM1_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG)

◆ LPTIM2_SEL

#define LPTIM2_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG)

◆ LPUART1_SEL

#define LPUART1_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)

CCIPR3 devices.

◆ MCO1_PRE

#define MCO1_PRE ( val ) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)

◆ MCO1_SEL

#define MCO1_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)

CFGR1 devices.

◆ MCO_PRE_DIV_1

#define MCO_PRE_DIV_1 0

◆ MCO_PRE_DIV_16

#define MCO_PRE_DIV_16 4

◆ MCO_PRE_DIV_2

#define MCO_PRE_DIV_2 1

◆ MCO_PRE_DIV_4

#define MCO_PRE_DIV_4 2

◆ MCO_PRE_DIV_8

#define MCO_PRE_DIV_8 3

◆ MCO_SEL_HCLK5

#define MCO_SEL_HCLK5 10

◆ MCO_SEL_HSE32

#define MCO_SEL_HSE32 4

◆ MCO_SEL_HSI16

#define MCO_SEL_HSI16 3

◆ MCO_SEL_LSE

#define MCO_SEL_LSE 7

◆ MCO_SEL_LSI

#define MCO_SEL_LSI 6

◆ MCO_SEL_PLL1PCLK

#define MCO_SEL_PLL1PCLK 8

◆ MCO_SEL_PLL1QCLK

#define MCO_SEL_PLL1QCLK 9

◆ MCO_SEL_PLL1RCLK

#define MCO_SEL_PLL1RCLK 5

◆ MCO_SEL_SYSCLKPRE

#define MCO_SEL_SYSCLKPRE 1

◆ RNG_SEL

#define RNG_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)

CCIPR2 devices.

◆ RTC_SEL

#define RTC_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 8, BCDR1_REG)

BCDR1 devices.

◆ SPI1_SEL

#define SPI1_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)

◆ SPI3_SEL

#define SPI3_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG)

◆ STM32_CLOCK_BUS_AHB1

#define STM32_CLOCK_BUS_AHB1 0x088

Bus clocks (Register address offsets)

◆ STM32_CLOCK_BUS_AHB2

#define STM32_CLOCK_BUS_AHB2 0x08C

◆ STM32_CLOCK_BUS_AHB4

#define STM32_CLOCK_BUS_AHB4 0x094

◆ STM32_CLOCK_BUS_AHB5

#define STM32_CLOCK_BUS_AHB5 0x098

◆ STM32_CLOCK_BUS_APB1

#define STM32_CLOCK_BUS_APB1 0x09C

◆ STM32_CLOCK_BUS_APB1_2

#define STM32_CLOCK_BUS_APB1_2 0x0A0

◆ STM32_CLOCK_BUS_APB2

#define STM32_CLOCK_BUS_APB2 0x0A4

◆ STM32_CLOCK_BUS_APB7

#define STM32_CLOCK_BUS_APB7 0x0A8

◆ STM32_PERIPH_BUS_MAX

#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB7

◆ STM32_PERIPH_BUS_MIN

#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1

◆ STM32_SRC_CLOCK_MAX

#define STM32_SRC_CLOCK_MAX STM32_SRC_SYSCLK

◆ STM32_SRC_CLOCK_MIN

#define STM32_SRC_CLOCK_MIN STM32_SRC_PLL1_P

◆ STM32_SRC_HCLK1

#define STM32_SRC_HCLK1 (STM32_SRC_HSI16 + 1)

Bus clock.

◆ STM32_SRC_HCLK5

#define STM32_SRC_HCLK5 (STM32_SRC_HCLK1 + 1)

◆ STM32_SRC_HSE

#define STM32_SRC_HSE (STM32_SRC_LSI + 1)

Peripheral clock sources.

System clock Fixed clocks

◆ STM32_SRC_HSI16

#define STM32_SRC_HSI16 (STM32_SRC_HSE + 1)

◆ STM32_SRC_PCLK1

#define STM32_SRC_PCLK1 (STM32_SRC_HCLK5 + 1)

◆ STM32_SRC_PCLK2

#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1)

◆ STM32_SRC_PCLK7

#define STM32_SRC_PCLK7 (STM32_SRC_PCLK2 + 1)

◆ STM32_SRC_PLL1_P

#define STM32_SRC_PLL1_P (STM32_SRC_PCLK7 + 1)

PLL outputs.

◆ STM32_SRC_PLL1_Q

#define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1)

◆ STM32_SRC_PLL1_R

#define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1)

◆ SYSTICK_SEL

#define SYSTICK_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)

◆ TIMIC_SEL

#define TIMIC_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG)

◆ USART1_SEL

#define USART1_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG)

Device clk sources selection helpers.

CCIPR1 devices

◆ USART2_SEL

#define USART2_SEL ( val ) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG)

Macros