Zephyr Project API 4.2.99
A Scalable Open Source RTOS
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stm32_clock_control.h
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1/*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2016 BayLibre, SAS
4 * Copyright (c) 2017-2022 Linaro Limited.
5 * Copyright (c) 2017 RnDity Sp. z o.o.
6 * Copyright (c) 2023 STMicroelectronics
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
11#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
12
14
15#if defined(CONFIG_SOC_SERIES_STM32C0X)
17#elif defined(CONFIG_SOC_SERIES_STM32F0X)
19#elif defined(CONFIG_SOC_SERIES_STM32F1X)
20#if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE)
22#else
24#endif
25#elif defined(CONFIG_SOC_SERIES_STM32F3X)
27#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
28 defined(CONFIG_SOC_SERIES_STM32F4X)
31#elif defined(CONFIG_SOC_SERIES_STM32F7X)
33#elif defined(CONFIG_SOC_SERIES_STM32G0X)
35#elif defined(CONFIG_SOC_SERIES_STM32G4X)
37#elif defined(CONFIG_SOC_SERIES_STM32L0X)
39#elif defined(CONFIG_SOC_SERIES_STM32L1X)
41#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
42 defined(CONFIG_SOC_SERIES_STM32L5X)
44#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
46#elif defined(CONFIG_SOC_SERIES_STM32WBX)
48#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
50#elif defined(CONFIG_SOC_SERIES_STM32WLX)
52#elif defined(CONFIG_SOC_SERIES_STM32H5X)
54#elif defined(CONFIG_SOC_SERIES_STM32H7X)
56#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
58#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
60#elif defined(CONFIG_SOC_SERIES_STM32N6X)
62#elif defined(CONFIG_SOC_SERIES_STM32U0X)
64#elif defined(CONFIG_SOC_SERIES_STM32U3X)
66#elif defined(CONFIG_SOC_SERIES_STM32U5X)
68#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
70#else
72#endif
73
75#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
76
79#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
80#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
81#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
82#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
83#define STM32_APB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb4_prescaler)
84#define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
85#define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
86#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
87#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
88#define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1)
89#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
90#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
91
92#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler)
93#define STM32_CORE_PRESCALER STM32_AHB_PRESCALER
94#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
95#define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER
96#endif
97
98#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
99#define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER
100#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
101#define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER
102#else
103#define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER
104#endif
105
106#define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler)
107#define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler)
108#define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler)
109
110#define STM32_TIMER_PRESCALER DT_PROP(DT_NODELABEL(rcc), timpre)
111
113#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
114#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), dcpre)
115#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
116#define STM32_PPRE1 DT_PROP(DT_NODELABEL(rcc), ppre1)
117#define STM32_PPRE2 DT_PROP(DT_NODELABEL(rcc), ppre2)
118#define STM32_PPRE4 DT_PROP(DT_NODELABEL(rcc), ppre4)
119#define STM32_PPRE5 DT_PROP(DT_NODELABEL(rcc), ppre5)
120#else
121#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
122#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
123#define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
124#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
125#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
126#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
127#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
128
130#define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div)
131
132#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
133
134/* To enable use of IS_ENABLED utility macro, these symbols
135 * should not be defined directly using DT_SAME_NODE.
136 */
137#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
138#define STM32_SYSCLK_SRC_PLL 1
139#endif
140#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
141#define STM32_SYSCLK_SRC_HSI 1
142#endif
143#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
144#define STM32_SYSCLK_SRC_HSE 1
145#endif
146#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
147#define STM32_SYSCLK_SRC_MSI 1
148#endif
149#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
150#define STM32_SYSCLK_SRC_MSIS 1
151#endif
152#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
153#define STM32_SYSCLK_SRC_CSI 1
154#endif
155#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(ic2))
156#define STM32_SYSCLK_SRC_IC2 1
157#endif
158
159#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32n6_rcc, okay)
160#if (DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(cpusw), 0), DT_NODELABEL(rcc)))
161#if (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSI)
162#define STM32_CPUCLK_SRC_HSI 1
163#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_MSI)
164#define STM32_CPUCLK_SRC_MSI 1
165#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSE)
166#define STM32_CPUCLK_SRC_HSE 1
167#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_IC1)
168#define STM32_CPUCLK_SRC_IC1 1
169#endif
170#endif /* cpusw clk source is rcc */
171
172#define STM32_TIMG_PRESCALER DT_PROP(DT_NODELABEL(rcc), timg_prescaler)
173#endif /* rcc node compatible st_stm32n6_rcc and okay */
174
177#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
178 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
179 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
180 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
181 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
182 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
183 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
184 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
185 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
186 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
187 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
188 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) || \
189 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32mp13_pll_clock, okay)
190#define STM32_PLL_ENABLED 1
191#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
192#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
193#define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
194#define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
195#define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
196#define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
197#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
198#define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
199#define STM32_PLL_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_s)
200#define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1)
201#define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn)
202#define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
203#endif
204
205#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay)
206#define STM32_PLLI2S_ENABLED 1
207#define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR
208#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
209#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
210#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
211#endif
212
213#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f411_plli2s_clock, okay)
214#define STM32_PLLI2S_ENABLED 1
215#define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m)
216#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
217#define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q)
218#define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1)
219#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
220#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
221#endif
222
223#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay)
224#define STM32_PLLSAI1_ENABLED 1
225#define STM32_PLLSAI1_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai1), div_m)
226#define STM32_PLLSAI1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai1), mul_n)
227#define STM32_PLLSAI1_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_p)
228#define STM32_PLLSAI1_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_p, 1)
229#define STM32_PLLSAI1_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_q)
230#define STM32_PLLSAI1_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_q, 1)
231#define STM32_PLLSAI1_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_r)
232#define STM32_PLLSAI1_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_r, 1)
233#endif
234
235#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay)
236#define STM32_PLLSAI2_ENABLED 1
237#define STM32_PLLSAI2_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai2), div_m)
238#define STM32_PLLSAI2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai2), mul_n)
239#define STM32_PLLSAI2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_p)
240#define STM32_PLLSAI2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_p, 1)
241#define STM32_PLLSAI2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_q)
242#define STM32_PLLSAI2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_q, 1)
243#define STM32_PLLSAI2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_r)
244#define STM32_PLLSAI2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_r, 1)
245#define STM32_PLLSAI2_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_divr)
246#define STM32_PLLSAI2_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_divr, 1)
247#endif
248
249#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
250 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
251 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) || \
252 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32mp13_pll_clock, okay)
253#define STM32_PLL2_ENABLED 1
254#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
255#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
256#define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p)
257#define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
258#define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q)
259#define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
260#define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r)
261#define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1)
262#define STM32_PLL2_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_s)
263#define STM32_PLL2_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_s, 1)
264#define STM32_PLL2_T_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_t)
265#define STM32_PLL2_T_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_t, 1)
266#define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn)
267#define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1)
268#endif
269
270#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
271 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
272 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) || \
273 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32mp13_pll_clock, okay)
274#define STM32_PLL3_ENABLED 1
275#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
276#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
277#define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
278#define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1)
279#define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
280#define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
281#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
282#define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1)
283#define STM32_PLL3_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_s)
284#define STM32_PLL3_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_s, 1)
285#define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn)
286#define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
287#endif
288
289#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32mp13_pll_clock, okay)
290#define STM32_PLL4_ENABLED 1
291#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
292#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
293#define STM32_PLL4_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_p)
294#define STM32_PLL4_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_p, 1)
295#define STM32_PLL4_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_q)
296#define STM32_PLL4_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_q, 1)
297#define STM32_PLL4_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_r)
298#define STM32_PLL4_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_r, 1)
299#define STM32_PLL4_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), fracn)
300#define STM32_PLL4_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll4), fracn, 1)
301#endif
302
303#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
304#define STM32_PLL_ENABLED 1
305#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)
306#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
307#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre)
308#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
309 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
310 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
311#define STM32_PLL_ENABLED 1
312#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
313#define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv)
314#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre)
315#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
316#define STM32_PLL_ENABLED 1
317#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
318#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
319#endif
320
321#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay)
322#define STM32_PLL2_ENABLED 1
323#define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul)
324#define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv)
325#endif
326
327#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)
328#define STM32_PLL1_ENABLED 1
329#define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m)
330#define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n)
331#define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1)
332#define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2)
333#endif
334
335#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32n6_pll_clock, okay)
336#define STM32_PLL2_ENABLED 1
337#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
338#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
339#define STM32_PLL2_P1_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p1)
340#define STM32_PLL2_P2_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p2)
341#endif
342
343#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32n6_pll_clock, okay)
344#define STM32_PLL3_ENABLED 1
345#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
346#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
347#define STM32_PLL3_P1_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p1)
348#define STM32_PLL3_P2_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p2)
349#endif
350
351#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32n6_pll_clock, okay)
352#define STM32_PLL4_ENABLED 1
353#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
354#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
355#define STM32_PLL4_P1_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p1)
356#define STM32_PLL4_P2_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p2)
357#endif
358
360#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \
361 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
362#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
363#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
364#define STM32_PLL_SRC_MSI 1
365#endif
366#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
367#define STM32_PLL_SRC_MSIS 1
368#endif
369#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
370#define STM32_PLL_SRC_HSI 1
371#endif
372#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
373#define STM32_PLL_SRC_CSI 1
374#endif
375#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
376#define STM32_PLL_SRC_HSE 1
377#endif
378#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
379#define STM32_PLL_SRC_PLL2 1
380#endif
381
382#endif
383
385#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \
386 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks)
387#define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
388#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
389#define STM32_PLL2_SRC_MSI 1
390#endif
391#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
392#define STM32_PLL2_SRC_MSIS 1
393#endif
394#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
395#define STM32_PLL2_SRC_HSI 1
396#endif
397#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
398#define STM32_PLL2_SRC_HSE 1
399#endif
400
401#endif
402
404#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \
405 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks)
406#define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
407#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
408#define STM32_PLL3_SRC_MSI 1
409#endif
410#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
411#define STM32_PLL3_SRC_MSIS 1
412#endif
413#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
414#define STM32_PLL3_SRC_HSI 1
415#endif
416#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
417#define STM32_PLL3_SRC_HSE 1
418#endif
419
420#endif
421
423#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll4), okay) && \
424 DT_NODE_HAS_PROP(DT_NODELABEL(pll4), clocks)
425#define DT_PLL4_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll4))
426#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
427#define STM32_PLL4_SRC_MSI 1
428#endif
429#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
430#define STM32_PLL4_SRC_HSI 1
431#endif
432#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
433#define STM32_PLL4_SRC_HSE 1
434#endif
435
436#endif
437
439#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai1), okay) && \
440 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), clocks)
441#define DT_PLLSAI1_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai1))
442#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
443#define STM32_PLLSAI1_SRC_MSI 1
444#endif
445#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
446#define STM32_PLLSAI1_SRC_HSI 1
447#endif
448#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
449#define STM32_PLLSAI1_SRC_HSE 1
450#endif
451
452#endif
453
455#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai2), okay) && \
456 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), clocks)
457#define DT_PLLSAI2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai2))
458#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
459#define STM32_PLLSAI2_SRC_MSI 1
460#endif
461#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
462#define STM32_PLLSAI2_SRC_HSI 1
463#endif
464#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
465#define STM32_PLLSAI2_SRC_HSE 1
466#endif
467
468#endif
469
470/* On STM32L4 series - PLL / PLLSAI1 and PLLSAI2 shared same source */
471#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
472 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
473 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI1_CLOCKS_CTRL)
474#error "On STM32L4 series, PLL / PLLSAI1 must have the same source"
475#endif
476#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
477 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
478 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
479#error "On STM32L4 series, PLL / PLLSAI2 must have the same source"
480#endif
481#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
482 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
483 !DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
484#error "On STM32L4 series, PLLSAI1 / PLLSAI2 must have the same source"
485#endif
486
489#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
490#define STM32_LSE_ENABLED 1
491#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
492#define STM32_LSE_DRIVING 0
493#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
494#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
495#define STM32_LSE_ENABLED 1
496#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
497#define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
498#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
499#else
500#define STM32_LSE_ENABLED 0
501#define STM32_LSE_FREQ 0
502#define STM32_LSE_DRIVING 0
503#define STM32_LSE_BYPASS 0
504#endif
505
506#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
507 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
508#define STM32_MSI_ENABLED 1
509#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
510#endif
511
512#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
513#define STM32_MSI_ENABLED 1
514#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
515#endif
516
517#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) || \
518 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u3_msi_clock, okay)
519#define STM32_MSIS_ENABLED 1
520#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
521#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
522#else
523#define STM32_MSIS_ENABLED 0
524#define STM32_MSIS_RANGE 0
525#define STM32_MSIS_PLL_MODE 0
526#endif
527
528#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) || \
529 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u3_msi_clock, okay)
530#define STM32_MSIK_ENABLED 1
531#define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
532#define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)
533#else
534#define STM32_MSIK_ENABLED 0
535#define STM32_MSIK_RANGE 0
536#define STM32_MSIK_PLL_MODE 0
537#endif
538
539#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
540#define STM32_CSI_ENABLED 1
541#define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
542#else
543#define STM32_CSI_FREQ 0
544#endif
545
546#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
547#define STM32_LSI_ENABLED 1
548#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
549#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay)
550#define STM32_LSI_ENABLED 1
551#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency)
552#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay)
553#define STM32_LSI_ENABLED 1
554#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency)
555#else
556#define STM32_LSI_FREQ 0
557#endif
558
559#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay)
560#define STM32_HSI_DIV_ENABLED 0
561#define STM32_HSI_ENABLED 1
562#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
563#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \
564 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32l0_hsi_clock, okay) \
565 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \
566 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) \
567 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32n6_hsi_clock, okay)
568#define STM32_HSI_DIV_ENABLED 1
569#define STM32_HSI_ENABLED 1
570#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
571#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
572#else
573#define STM32_HSI_DIV_ENABLED 0
574#define STM32_HSI_DIVISOR 1
575#define STM32_HSI_FREQ 0
576#endif
577
578#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay)
579#define STM32_HSE_ENABLED 1
580#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
581#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
582#define STM32_HSE_ENABLED 1
583#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
584#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
585#define STM32_HSE_CSS DT_PROP(DT_NODELABEL(clk_hse), css_enabled)
586#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
587#define STM32_HSE_ENABLED 1
588#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
589#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
590#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
591#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay)
592#define STM32_HSE_ENABLED 1
593#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
594#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
595#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32n6_hse_clock, okay)
596#define STM32_HSE_ENABLED 1
597#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
598#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
599#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
600#else
601#define STM32_HSE_FREQ 0
602#endif
603
604#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay)
605#define STM32_HSI48_ENABLED 1
606#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
607#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), st_stm32_hsi48_clock, okay)
608#define STM32_HSI48_ENABLED 1
609#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
610#define STM32_HSI48_CRS_USB_SOF DT_PROP(DT_NODELABEL(clk_hsi48), crs_usb_sof)
611#endif
612
613#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay)
614#define STM32_CKPER_ENABLED 1
615#endif
616
617#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(cpusw), st_stm32_clock_mux, okay)
618#define STM32_CPUSW_ENABLED 1
619#endif
620
621#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic1), st_stm32n6_ic_clock_mux, okay)
622#define STM32_IC1_ENABLED 1
623#define STM32_IC1_PLL_SRC DT_PROP(DT_NODELABEL(ic1), pll_src)
624#define STM32_IC1_DIV DT_PROP(DT_NODELABEL(ic1), ic_div)
625#endif
626
627#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic2), st_stm32n6_ic_clock_mux, okay)
628#define STM32_IC2_ENABLED 1
629#define STM32_IC2_PLL_SRC DT_PROP(DT_NODELABEL(ic2), pll_src)
630#define STM32_IC2_DIV DT_PROP(DT_NODELABEL(ic2), ic_div)
631#endif
632
633#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic3), st_stm32n6_ic_clock_mux, okay)
634#define STM32_IC3_ENABLED 1
635#define STM32_IC3_PLL_SRC DT_PROP(DT_NODELABEL(ic3), pll_src)
636#define STM32_IC3_DIV DT_PROP(DT_NODELABEL(ic3), ic_div)
637#endif
638
639#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic4), st_stm32n6_ic_clock_mux, okay)
640#define STM32_IC4_ENABLED 1
641#define STM32_IC4_PLL_SRC DT_PROP(DT_NODELABEL(ic4), pll_src)
642#define STM32_IC4_DIV DT_PROP(DT_NODELABEL(ic4), ic_div)
643#endif
644
645#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic5), st_stm32n6_ic_clock_mux, okay)
646#define STM32_IC5_ENABLED 1
647#define STM32_IC5_PLL_SRC DT_PROP(DT_NODELABEL(ic5), pll_src)
648#define STM32_IC5_DIV DT_PROP(DT_NODELABEL(ic5), ic_div)
649#endif
650
651#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic6), st_stm32n6_ic_clock_mux, okay)
652#define STM32_IC6_ENABLED 1
653#define STM32_IC6_PLL_SRC DT_PROP(DT_NODELABEL(ic6), pll_src)
654#define STM32_IC6_DIV DT_PROP(DT_NODELABEL(ic6), ic_div)
655#endif
656
657#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic7), st_stm32n6_ic_clock_mux, okay)
658#define STM32_IC7_ENABLED 1
659#define STM32_IC7_PLL_SRC DT_PROP(DT_NODELABEL(ic7), pll_src)
660#define STM32_IC7_DIV DT_PROP(DT_NODELABEL(ic7), ic_div)
661#endif
662
663#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic8), st_stm32n6_ic_clock_mux, okay)
664#define STM32_IC8_ENABLED 1
665#define STM32_IC8_PLL_SRC DT_PROP(DT_NODELABEL(ic8), pll_src)
666#define STM32_IC8_DIV DT_PROP(DT_NODELABEL(ic8), ic_div)
667#endif
668
669#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic9), st_stm32n6_ic_clock_mux, okay)
670#define STM32_IC9_ENABLED 1
671#define STM32_IC9_PLL_SRC DT_PROP(DT_NODELABEL(ic9), pll_src)
672#define STM32_IC9_DIV DT_PROP(DT_NODELABEL(ic9), ic_div)
673#endif
674
675#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic10), st_stm32n6_ic_clock_mux, okay)
676#define STM32_IC10_ENABLED 1
677#define STM32_IC10_PLL_SRC DT_PROP(DT_NODELABEL(ic10), pll_src)
678#define STM32_IC10_DIV DT_PROP(DT_NODELABEL(ic10), ic_div)
679#endif
680
681#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic11), st_stm32n6_ic_clock_mux, okay)
682#define STM32_IC11_ENABLED 1
683#define STM32_IC11_PLL_SRC DT_PROP(DT_NODELABEL(ic11), pll_src)
684#define STM32_IC11_DIV DT_PROP(DT_NODELABEL(ic11), ic_div)
685#endif
686
687#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic12), st_stm32n6_ic_clock_mux, okay)
688#define STM32_IC12_ENABLED 1
689#define STM32_IC12_PLL_SRC DT_PROP(DT_NODELABEL(ic12), pll_src)
690#define STM32_IC12_DIV DT_PROP(DT_NODELABEL(ic12), ic_div)
691#endif
692
693#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic13), st_stm32n6_ic_clock_mux, okay)
694#define STM32_IC13_ENABLED 1
695#define STM32_IC13_PLL_SRC DT_PROP(DT_NODELABEL(ic13), pll_src)
696#define STM32_IC13_DIV DT_PROP(DT_NODELABEL(ic13), ic_div)
697#endif
698
699#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic14), st_stm32n6_ic_clock_mux, okay)
700#define STM32_IC14_ENABLED 1
701#define STM32_IC14_PLL_SRC DT_PROP(DT_NODELABEL(ic14), pll_src)
702#define STM32_IC14_DIV DT_PROP(DT_NODELABEL(ic14), ic_div)
703#endif
704
705#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic15), st_stm32n6_ic_clock_mux, okay)
706#define STM32_IC15_ENABLED 1
707#define STM32_IC15_PLL_SRC DT_PROP(DT_NODELABEL(ic15), pll_src)
708#define STM32_IC15_DIV DT_PROP(DT_NODELABEL(ic15), ic_div)
709#endif
710
711#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic16), st_stm32n6_ic_clock_mux, okay)
712#define STM32_IC16_ENABLED 1
713#define STM32_IC16_PLL_SRC DT_PROP(DT_NODELABEL(ic16), pll_src)
714#define STM32_IC16_DIV DT_PROP(DT_NODELABEL(ic16), ic_div)
715#endif
716
717#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic17), st_stm32n6_ic_clock_mux, okay)
718#define STM32_IC17_ENABLED 1
719#define STM32_IC17_PLL_SRC DT_PROP(DT_NODELABEL(ic17), pll_src)
720#define STM32_IC17_DIV DT_PROP(DT_NODELABEL(ic17), ic_div)
721#endif
722
723#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic18), st_stm32n6_ic_clock_mux, okay)
724#define STM32_IC18_ENABLED 1
725#define STM32_IC18_PLL_SRC DT_PROP(DT_NODELABEL(ic18), pll_src)
726#define STM32_IC18_DIV DT_PROP(DT_NODELABEL(ic18), ic_div)
727#endif
728
729#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic19), st_stm32n6_ic_clock_mux, okay)
730#define STM32_IC19_ENABLED 1
731#define STM32_IC19_PLL_SRC DT_PROP(DT_NODELABEL(ic19), pll_src)
732#define STM32_IC19_DIV DT_PROP(DT_NODELABEL(ic19), ic_div)
733#endif
734
735#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic20), st_stm32n6_ic_clock_mux, okay)
736#define STM32_IC20_ENABLED 1
737#define STM32_IC20_PLL_SRC DT_PROP(DT_NODELABEL(ic20), pll_src)
738#define STM32_IC20_DIV DT_PROP(DT_NODELABEL(ic20), ic_div)
739#endif
740
748
751#define STM32_CLOCK_INFO(clk_index, node_id) \
752 { \
753 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \
754 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) & \
755 GENMASK(STM32_CLOCK_DIV_SHIFT - 1, 0), \
756 .div = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) >> \
757 STM32_CLOCK_DIV_SHIFT, \
758 }
759#define STM32_DT_CLOCKS(node_id) \
760 { \
761 LISTIFY(DT_NUM_CLOCKS(node_id), \
762 STM32_CLOCK_INFO, (,), node_id) \
763 }
764
765#define STM32_DT_INST_CLOCKS(inst) \
766 STM32_DT_CLOCKS(DT_DRV_INST(inst))
767
768#define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) ||
769#define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \
770 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0)
771
772#define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) ||
773#define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \
774 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0)
775
783#define STM32_DT_CLKSEL_REG_GET(clock) \
784 (((clock) >> STM32_DT_CLKSEL_REG_SHIFT) & STM32_DT_CLKSEL_REG_MASK)
785
791#define STM32_DT_CLKSEL_SHIFT_GET(clock) \
792 (((clock) >> STM32_DT_CLKSEL_SHIFT_SHIFT) & STM32_DT_CLKSEL_SHIFT_MASK)
793
799#define STM32_DT_CLKSEL_MASK_GET(clock) \
800 (((clock) >> STM32_DT_CLKSEL_MASK_SHIFT) & STM32_DT_CLKSEL_MASK_MASK)
801
807#define STM32_DT_CLKSEL_VAL_GET(clock) \
808 (((clock) >> STM32_DT_CLKSEL_VAL_SHIFT) & STM32_DT_CLKSEL_VAL_MASK)
809
810#if defined(STM32_HSE_CSS)
819void stm32_hse_css_callback(void);
820#endif
821
822#ifdef CONFIG_SOC_SERIES_STM32WB0X
827typedef void (*lsi_update_cb_t)(uint32_t new_lsi_frequency);
828
840int stm32wb0_register_lsi_update_callback(lsi_update_cb_t cb);
841#endif /* CONFIG_SOC_SERIES_STM32WB0X */
842
843#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */
Public Clock Control APIs.
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
#define STM32_CLOCK_DIV_SHIFT
Definition stm32_clock.h:27
Driver structure definition.
Definition stm32_clock_control.h:743
uint32_t div
Definition stm32_clock_control.h:745
uint32_t bus
Definition stm32_clock_control.h:744
uint32_t enr
Definition stm32_clock_control.h:746