Zephyr Project API 4.2.99
A Scalable Open Source RTOS
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stm32_clock_control.h
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1/*
2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
3 * Copyright (c) 2016 BayLibre, SAS
4 * Copyright (c) 2017-2022 Linaro Limited.
5 * Copyright (c) 2017 RnDity Sp. z o.o.
6 * Copyright (c) 2023 STMicroelectronics
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
11#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_
12
13#include <zephyr/drivers/clock_control.h>
14
15/* Retrieve the main system clock from DTS. */
16#define STM32_HCLK_FREQUENCY DT_PROP(DT_NODELABEL(rcc), clock_frequency)
17
18#if defined(CONFIG_SOC_SERIES_STM32C0X)
19#include <zephyr/dt-bindings/clock/stm32c0_clock.h>
20#elif defined(CONFIG_SOC_SERIES_STM32F0X)
21#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
22#elif defined(CONFIG_SOC_SERIES_STM32F1X)
23#if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE)
24#include <zephyr/dt-bindings/clock/stm32f10x_clock.h>
25#else
26#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
27#endif
28#elif defined(CONFIG_SOC_SERIES_STM32F3X)
29#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
30#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
31 defined(CONFIG_SOC_SERIES_STM32F4X)
32#include <zephyr/dt-bindings/clock/stm32f4_clock.h>
33#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
34#elif defined(CONFIG_SOC_SERIES_STM32F7X)
35#include <zephyr/dt-bindings/clock/stm32f7_clock.h>
36#elif defined(CONFIG_SOC_SERIES_STM32G0X)
37#include <zephyr/dt-bindings/clock/stm32g0_clock.h>
38#elif defined(CONFIG_SOC_SERIES_STM32G4X)
39#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
40#elif defined(CONFIG_SOC_SERIES_STM32L0X)
41#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
42#elif defined(CONFIG_SOC_SERIES_STM32L1X)
43#include <zephyr/dt-bindings/clock/stm32l1_clock.h>
44#elif defined(CONFIG_SOC_SERIES_STM32L4X)
45#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
46#elif defined(CONFIG_SOC_SERIES_STM32L5X)
47#include <zephyr/dt-bindings/clock/stm32l5_clock.h>
48#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
49#include <zephyr/dt-bindings/clock/stm32mp2_clock.h>
50#elif defined(CONFIG_SOC_SERIES_STM32WBX)
51#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
52#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
53#include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
54#elif defined(CONFIG_SOC_SERIES_STM32WLX)
55#include <zephyr/dt-bindings/clock/stm32wl_clock.h>
56#elif defined(CONFIG_SOC_SERIES_STM32H5X)
57#include <zephyr/dt-bindings/clock/stm32h5_clock.h>
58#elif defined(CONFIG_SOC_SERIES_STM32H7X)
59#include <zephyr/dt-bindings/clock/stm32h7_clock.h>
60#elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
61#include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
62#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
63#include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
64#elif defined(CONFIG_SOC_SERIES_STM32N6X)
65#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
66#elif defined(CONFIG_SOC_SERIES_STM32U0X)
67#include <zephyr/dt-bindings/clock/stm32u0_clock.h>
68#elif defined(CONFIG_SOC_SERIES_STM32U3X)
69#include <zephyr/dt-bindings/clock/stm32u3_clock.h>
70#elif defined(CONFIG_SOC_SERIES_STM32U5X)
71#include <zephyr/dt-bindings/clock/stm32u5_clock.h>
72#elif defined(CONFIG_SOC_SERIES_STM32WBAX)
73#include <zephyr/dt-bindings/clock/stm32wba_clock.h>
74#else
75#include <zephyr/dt-bindings/clock/stm32_clock.h>
76#endif
77
79#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
80
83#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
84#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
85#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
86#define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
87#define STM32_APB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb4_prescaler)
88#define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
89#define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
90#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
91#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
92#define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1)
93#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
94#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
95
96#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler)
97#define STM32_CORE_PRESCALER STM32_AHB_PRESCALER
98#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
99#define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER
100#endif
101
102#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
103#define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER
104#elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
105#define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER
106#else
107#define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER
108#endif
109
110#define STM32_TIMER_PRESCALER DT_PROP(DT_NODELABEL(rcc), timpre)
111
113#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
114#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), dcpre)
115#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
116#define STM32_PPRE1 DT_PROP(DT_NODELABEL(rcc), ppre1)
117#define STM32_PPRE2 DT_PROP(DT_NODELABEL(rcc), ppre2)
118#define STM32_PPRE4 DT_PROP(DT_NODELABEL(rcc), ppre4)
119#define STM32_PPRE5 DT_PROP(DT_NODELABEL(rcc), ppre5)
120#else
121#define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre)
122#define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre)
123#define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1)
124#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
125#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
126#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
127#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
128
130#define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div)
131
132#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
133
134/* To enable use of IS_ENABLED utility macro, these symbols
135 * should not be defined directly using DT_SAME_NODE.
136 */
137#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
138#define STM32_SYSCLK_SRC_PLL 1
139#endif
140#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
141#define STM32_SYSCLK_SRC_HSI 1
142#endif
143#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
144#define STM32_SYSCLK_SRC_HSE 1
145#endif
146#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
147#define STM32_SYSCLK_SRC_MSI 1
148#endif
149#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
150#define STM32_SYSCLK_SRC_MSIS 1
151#endif
152#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
153#define STM32_SYSCLK_SRC_CSI 1
154#endif
155#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(ic2))
156#define STM32_SYSCLK_SRC_IC2 1
157#endif
158
159#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32n6_rcc, okay)
160#if (DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(cpusw), 0), DT_NODELABEL(rcc)))
161#if (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSI)
162#define STM32_CPUCLK_SRC_HSI 1
163#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_MSI)
164#define STM32_CPUCLK_SRC_MSI 1
165#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSE)
166#define STM32_CPUCLK_SRC_HSE 1
167#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_IC1)
168#define STM32_CPUCLK_SRC_IC1 1
169#endif
170#endif /* cpusw clk source is rcc */
171
172#define STM32_TIMG_PRESCALER DT_PROP(DT_NODELABEL(rcc), timg_prescaler)
173#endif /* rcc node compatible st_stm32n6_rcc and okay */
174
176#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk48), st_stm32_clock_mux, okay)
177#define STM32_CK48_ENABLED 1
178#endif
179
182#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
183 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \
184 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \
185 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \
186 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \
187 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \
188 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \
189 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \
190 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
191 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
192 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
193 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) || \
194 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32mp13_pll_clock, okay)
195#define STM32_PLL_ENABLED 1
196#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
197#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
198#define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p)
199#define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1)
200#define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q)
201#define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1)
202#define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r)
203#define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1)
204#define STM32_PLL_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_s)
205#define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1)
206#define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn)
207#define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1)
208#endif
209
210#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay)
211#define STM32_PLLI2S_ENABLED 1
212#define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR
213#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
214#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
215#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
216#endif
217
218#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f411_plli2s_clock, okay)
219#define STM32_PLLI2S_ENABLED 1
220#define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m)
221#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
222#define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q)
223#define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1)
224#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
225#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
226#endif
227
228#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay)
229#define STM32_PLLSAI_ENABLED 1
230#define STM32_PLLSAI_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai), div_m)
231#define STM32_PLLSAI_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai), mul_n)
232#define STM32_PLLSAI_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_p)
233#define STM32_PLLSAI_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_p, 1)
234#define STM32_PLLSAI_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_q)
235#define STM32_PLLSAI_DIVQ_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divq)
236#if (STM32_PLLSAI_Q_ENABLED && !STM32_PLLSAI_DIVQ_ENABLED) || \
237 (!STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED)
238#error "On STM32F4/STM32F7, both div_q and div_divq must be present if one of them is present"
239#endif
240#define STM32_PLLSAI_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_q, 1)
241#define STM32_PLLSAI_DIVQ_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divq, 1)
242#define STM32_PLLSAI_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_r)
243#define STM32_PLLSAI_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divr)
244#if (STM32_PLLSAI_R_ENABLED && !STM32_PLLSAI_DIVR_ENABLED) || \
245 (!STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED)
246#error "On STM32F4/STM32F7, both div_r and div_divr must be present if one of them is present"
247#endif
248#define STM32_PLLSAI_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_r, 1)
249#define STM32_PLLSAI_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divr, 1)
250#endif
251
252#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay)
253#define STM32_PLLSAI1_ENABLED 1
254#define STM32_PLLSAI1_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai1), div_m)
255#define STM32_PLLSAI1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai1), mul_n)
256#define STM32_PLLSAI1_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_p)
257#define STM32_PLLSAI1_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_p, 1)
258#define STM32_PLLSAI1_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_q)
259#define STM32_PLLSAI1_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_q, 1)
260#define STM32_PLLSAI1_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), div_r)
261#define STM32_PLLSAI1_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai1), div_r, 1)
262#endif
263
264#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay)
265#define STM32_PLLSAI2_ENABLED 1
266#define STM32_PLLSAI2_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai2), div_m)
267#define STM32_PLLSAI2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai2), mul_n)
268#define STM32_PLLSAI2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_p)
269#define STM32_PLLSAI2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_p, 1)
270#define STM32_PLLSAI2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_q)
271#define STM32_PLLSAI2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_q, 1)
272#define STM32_PLLSAI2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_r)
273#define STM32_PLLSAI2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_r, 1)
274#define STM32_PLLSAI2_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), div_divr)
275#define STM32_PLLSAI2_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai2), div_divr, 1)
276#endif
277
278#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
279 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
280 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) || \
281 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32mp13_pll_clock, okay)
282#define STM32_PLL2_ENABLED 1
283#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
284#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
285#define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p)
286#define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
287#define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q)
288#define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
289#define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r)
290#define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1)
291#define STM32_PLL2_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_s)
292#define STM32_PLL2_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_s, 1)
293#define STM32_PLL2_T_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_t)
294#define STM32_PLL2_T_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_t, 1)
295#define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn)
296#define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1)
297#endif
298
299#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
300 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
301 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) || \
302 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32mp13_pll_clock, okay)
303#define STM32_PLL3_ENABLED 1
304#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
305#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
306#define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p)
307#define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1)
308#define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q)
309#define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1)
310#define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
311#define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1)
312#define STM32_PLL3_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_s)
313#define STM32_PLL3_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_s, 1)
314#define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn)
315#define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
316#endif
317
318#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32mp13_pll_clock, okay)
319#define STM32_PLL4_ENABLED 1
320#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
321#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
322#define STM32_PLL4_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_p)
323#define STM32_PLL4_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_p, 1)
324#define STM32_PLL4_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_q)
325#define STM32_PLL4_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_q, 1)
326#define STM32_PLL4_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_r)
327#define STM32_PLL4_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_r, 1)
328#define STM32_PLL4_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), fracn)
329#define STM32_PLL4_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll4), fracn, 1)
330#endif
331
332#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
333#define STM32_PLL_ENABLED 1
334#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)
335#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
336#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre)
337#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
338 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \
339 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay)
340#define STM32_PLL_ENABLED 1
341#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
342#define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv)
343#define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre)
344#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
345#define STM32_PLL_ENABLED 1
346#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
347#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
348#endif
349
350#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay)
351#define STM32_PLL2_ENABLED 1
352#define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul)
353#define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv)
354#endif
355
356#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)
357#define STM32_PLL1_ENABLED 1
358#define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m)
359#define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n)
360#define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1)
361#define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2)
362#endif
363
364#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32n6_pll_clock, okay)
365#define STM32_PLL2_ENABLED 1
366#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
367#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
368#define STM32_PLL2_P1_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p1)
369#define STM32_PLL2_P2_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_p2)
370#endif
371
372#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32n6_pll_clock, okay)
373#define STM32_PLL3_ENABLED 1
374#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
375#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
376#define STM32_PLL3_P1_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p1)
377#define STM32_PLL3_P2_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_p2)
378#endif
379
380#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32n6_pll_clock, okay)
381#define STM32_PLL4_ENABLED 1
382#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
383#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
384#define STM32_PLL4_P1_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p1)
385#define STM32_PLL4_P2_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_p2)
386#endif
387
389#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \
390 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
391#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
392#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
393#define STM32_PLL_SRC_MSI 1
394#endif
395#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
396#define STM32_PLL_SRC_MSIS 1
397#endif
398#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
399#define STM32_PLL_SRC_HSI 1
400#endif
401#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
402#define STM32_PLL_SRC_CSI 1
403#endif
404#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
405#define STM32_PLL_SRC_HSE 1
406#endif
407#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
408#define STM32_PLL_SRC_PLL2 1
409#endif
410
411#endif
412
414#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \
415 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks)
416#define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
417#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
418#define STM32_PLL2_SRC_MSI 1
419#endif
420#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
421#define STM32_PLL2_SRC_MSIS 1
422#endif
423#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
424#define STM32_PLL2_SRC_HSI 1
425#endif
426#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
427#define STM32_PLL2_SRC_HSE 1
428#endif
429
430#endif
431
433#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \
434 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks)
435#define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
436#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
437#define STM32_PLL3_SRC_MSI 1
438#endif
439#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
440#define STM32_PLL3_SRC_MSIS 1
441#endif
442#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
443#define STM32_PLL3_SRC_HSI 1
444#endif
445#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
446#define STM32_PLL3_SRC_HSE 1
447#endif
448
449#endif
450
452#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll4), okay) && \
453 DT_NODE_HAS_PROP(DT_NODELABEL(pll4), clocks)
454#define DT_PLL4_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll4))
455#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
456#define STM32_PLL4_SRC_MSI 1
457#endif
458#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
459#define STM32_PLL4_SRC_HSI 1
460#endif
461#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
462#define STM32_PLL4_SRC_HSE 1
463#endif
464
465#endif
466
468#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai), okay) && \
469 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), clocks)
470#define DT_PLLSAI_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai))
471#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
472#define STM32_PLLSAI_SRC_HSI 1
473#endif
474#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
475#define STM32_PLLSAI_SRC_HSE 1
476#endif
477
478#endif
479
481#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai1), okay) && \
482 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), clocks)
483#define DT_PLLSAI1_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai1))
484#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
485#define STM32_PLLSAI1_SRC_MSI 1
486#endif
487#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
488#define STM32_PLLSAI1_SRC_HSI 1
489#endif
490#if DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
491#define STM32_PLLSAI1_SRC_HSE 1
492#endif
493
494#endif
495
497#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai2), okay) && \
498 DT_NODE_HAS_PROP(DT_NODELABEL(pllsai2), clocks)
499#define DT_PLLSAI2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai2))
500#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
501#define STM32_PLLSAI2_SRC_MSI 1
502#endif
503#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
504#define STM32_PLLSAI2_SRC_HSI 1
505#endif
506#if DT_SAME_NODE(DT_PLLSAI2_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
507#define STM32_PLLSAI2_SRC_HSE 1
508#endif
509
510#endif
511
512/* On STM32F4 series - PLL and PLLSAI share the same source */
513#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) && \
514 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
515 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
516#error "On STM32F4 series, PLL and PLLSAI must have the same source"
517#endif
518
519/* On STM32F7 series - PLL and PLLSAI share the same source */
520#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) && \
521 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \
522 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL)
523#error "On STM32F7 series, PLL and PLLSAI must have the same source"
524#endif
525
526/* On STM32L4 series - PLL / PLLSAI1 and PLLSAI2 shared same source */
527#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
528 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
529 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI1_CLOCKS_CTRL)
530#error "On STM32L4 series, PLL / PLLSAI1 must have the same source"
531#endif
532#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \
533 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
534 !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
535#error "On STM32L4 series, PLL / PLLSAI2 must have the same source"
536#endif
537#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \
538 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai2), st_stm32l4_pllsai_clock, okay) && \
539 !DT_SAME_NODE(DT_PLLSAI1_CLOCKS_CTRL, DT_PLLSAI2_CLOCKS_CTRL)
540#error "On STM32L4 series, PLLSAI1 / PLLSAI2 must have the same source"
541#endif
542
545#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
546#define STM32_LSE_ENABLED 1
547#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
548#define STM32_LSE_DRIVING 0
549#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
550#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
551#define STM32_LSE_ENABLED 1
552#define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
553#define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
554#define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
555#else
556#define STM32_LSE_ENABLED 0
557#define STM32_LSE_FREQ 0
558#define STM32_LSE_DRIVING 0
559#define STM32_LSE_BYPASS 0
560#endif
561
562#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
563 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
564#define STM32_MSI_ENABLED 1
565#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
566#endif
567
568#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
569#define STM32_MSI_ENABLED 1
570#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
571#endif
572
573#if defined(CONFIG_SOC_SERIES_STM32L4X) && STM32_MSI_PLL_MODE && !STM32_LSE_ENABLED
574#error "On STM32L4 series, MSI PLL mode requires LSE to be enabled"
575#endif
576
577#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) || \
578 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u3_msi_clock, okay)
579#define STM32_MSIS_ENABLED 1
580#define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range)
581#define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode)
582#else
583#define STM32_MSIS_ENABLED 0
584#define STM32_MSIS_RANGE 0
585#define STM32_MSIS_PLL_MODE 0
586#endif
587
588#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) || \
589 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u3_msi_clock, okay)
590#define STM32_MSIK_ENABLED 1
591#define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range)
592#define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode)
593#else
594#define STM32_MSIK_ENABLED 0
595#define STM32_MSIK_RANGE 0
596#define STM32_MSIK_PLL_MODE 0
597#endif
598
599#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay)
600#define STM32_CSI_ENABLED 1
601#define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
602#else
603#define STM32_CSI_FREQ 0
604#endif
605
606#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay)
607#define STM32_LSI_ENABLED 1
608#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
609#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay)
610#define STM32_LSI_ENABLED 1
611#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency)
612#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay)
613#define STM32_LSI_ENABLED 1
614#define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency)
615#else
616#define STM32_LSI_FREQ 0
617#endif
618
619#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay)
620#define STM32_HSI_DIV_ENABLED 0
621#define STM32_HSI_ENABLED 1
622#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
623#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \
624 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32l0_hsi_clock, okay) \
625 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \
626 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) \
627 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32n6_hsi_clock, okay)
628#define STM32_HSI_DIV_ENABLED 1
629#define STM32_HSI_ENABLED 1
630#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
631#define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
632#else
633#define STM32_HSI_DIV_ENABLED 0
634#define STM32_HSI_DIVISOR 1
635#define STM32_HSI_FREQ 0
636#endif
637
638#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay)
639#define STM32_HSE_ENABLED 1
640#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
641#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
642#define STM32_HSE_ENABLED 1
643#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
644#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
645#define STM32_HSE_CSS DT_PROP(DT_NODELABEL(clk_hse), css_enabled)
646#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
647#define STM32_HSE_ENABLED 1
648#define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo)
649#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
650#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
651#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay)
652#define STM32_HSE_ENABLED 1
653#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
654#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
655#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32n6_hse_clock, okay)
656#define STM32_HSE_ENABLED 1
657#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
658#define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
659#define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
660#else
661#define STM32_HSE_FREQ 0
662#endif
663
664#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay)
665#define STM32_HSI48_ENABLED 1
666#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
667#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), st_stm32_hsi48_clock, okay)
668#define STM32_HSI48_ENABLED 1
669#define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency)
670#define STM32_HSI48_CRS_USB_SOF DT_PROP(DT_NODELABEL(clk_hsi48), crs_usb_sof)
671#endif
672
673#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay)
674#define STM32_CKPER_ENABLED 1
675#endif
676
677#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(cpusw), st_stm32_clock_mux, okay)
678#define STM32_CPUSW_ENABLED 1
679#endif
680
681#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic1), st_stm32n6_ic_clock_mux, okay)
682#define STM32_IC1_ENABLED 1
683#define STM32_IC1_PLL_SRC DT_PROP(DT_NODELABEL(ic1), pll_src)
684#define STM32_IC1_DIV DT_PROP(DT_NODELABEL(ic1), ic_div)
685#endif
686
687#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic2), st_stm32n6_ic_clock_mux, okay)
688#define STM32_IC2_ENABLED 1
689#define STM32_IC2_PLL_SRC DT_PROP(DT_NODELABEL(ic2), pll_src)
690#define STM32_IC2_DIV DT_PROP(DT_NODELABEL(ic2), ic_div)
691#endif
692
693#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic3), st_stm32n6_ic_clock_mux, okay)
694#define STM32_IC3_ENABLED 1
695#define STM32_IC3_PLL_SRC DT_PROP(DT_NODELABEL(ic3), pll_src)
696#define STM32_IC3_DIV DT_PROP(DT_NODELABEL(ic3), ic_div)
697#endif
698
699#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic4), st_stm32n6_ic_clock_mux, okay)
700#define STM32_IC4_ENABLED 1
701#define STM32_IC4_PLL_SRC DT_PROP(DT_NODELABEL(ic4), pll_src)
702#define STM32_IC4_DIV DT_PROP(DT_NODELABEL(ic4), ic_div)
703#endif
704
705#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic5), st_stm32n6_ic_clock_mux, okay)
706#define STM32_IC5_ENABLED 1
707#define STM32_IC5_PLL_SRC DT_PROP(DT_NODELABEL(ic5), pll_src)
708#define STM32_IC5_DIV DT_PROP(DT_NODELABEL(ic5), ic_div)
709#endif
710
711#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic6), st_stm32n6_ic_clock_mux, okay)
712#define STM32_IC6_ENABLED 1
713#define STM32_IC6_PLL_SRC DT_PROP(DT_NODELABEL(ic6), pll_src)
714#define STM32_IC6_DIV DT_PROP(DT_NODELABEL(ic6), ic_div)
715#endif
716
717#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic7), st_stm32n6_ic_clock_mux, okay)
718#define STM32_IC7_ENABLED 1
719#define STM32_IC7_PLL_SRC DT_PROP(DT_NODELABEL(ic7), pll_src)
720#define STM32_IC7_DIV DT_PROP(DT_NODELABEL(ic7), ic_div)
721#endif
722
723#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic8), st_stm32n6_ic_clock_mux, okay)
724#define STM32_IC8_ENABLED 1
725#define STM32_IC8_PLL_SRC DT_PROP(DT_NODELABEL(ic8), pll_src)
726#define STM32_IC8_DIV DT_PROP(DT_NODELABEL(ic8), ic_div)
727#endif
728
729#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic9), st_stm32n6_ic_clock_mux, okay)
730#define STM32_IC9_ENABLED 1
731#define STM32_IC9_PLL_SRC DT_PROP(DT_NODELABEL(ic9), pll_src)
732#define STM32_IC9_DIV DT_PROP(DT_NODELABEL(ic9), ic_div)
733#endif
734
735#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic10), st_stm32n6_ic_clock_mux, okay)
736#define STM32_IC10_ENABLED 1
737#define STM32_IC10_PLL_SRC DT_PROP(DT_NODELABEL(ic10), pll_src)
738#define STM32_IC10_DIV DT_PROP(DT_NODELABEL(ic10), ic_div)
739#endif
740
741#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic11), st_stm32n6_ic_clock_mux, okay)
742#define STM32_IC11_ENABLED 1
743#define STM32_IC11_PLL_SRC DT_PROP(DT_NODELABEL(ic11), pll_src)
744#define STM32_IC11_DIV DT_PROP(DT_NODELABEL(ic11), ic_div)
745#endif
746
747#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic12), st_stm32n6_ic_clock_mux, okay)
748#define STM32_IC12_ENABLED 1
749#define STM32_IC12_PLL_SRC DT_PROP(DT_NODELABEL(ic12), pll_src)
750#define STM32_IC12_DIV DT_PROP(DT_NODELABEL(ic12), ic_div)
751#endif
752
753#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic13), st_stm32n6_ic_clock_mux, okay)
754#define STM32_IC13_ENABLED 1
755#define STM32_IC13_PLL_SRC DT_PROP(DT_NODELABEL(ic13), pll_src)
756#define STM32_IC13_DIV DT_PROP(DT_NODELABEL(ic13), ic_div)
757#endif
758
759#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic14), st_stm32n6_ic_clock_mux, okay)
760#define STM32_IC14_ENABLED 1
761#define STM32_IC14_PLL_SRC DT_PROP(DT_NODELABEL(ic14), pll_src)
762#define STM32_IC14_DIV DT_PROP(DT_NODELABEL(ic14), ic_div)
763#endif
764
765#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic15), st_stm32n6_ic_clock_mux, okay)
766#define STM32_IC15_ENABLED 1
767#define STM32_IC15_PLL_SRC DT_PROP(DT_NODELABEL(ic15), pll_src)
768#define STM32_IC15_DIV DT_PROP(DT_NODELABEL(ic15), ic_div)
769#endif
770
771#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic16), st_stm32n6_ic_clock_mux, okay)
772#define STM32_IC16_ENABLED 1
773#define STM32_IC16_PLL_SRC DT_PROP(DT_NODELABEL(ic16), pll_src)
774#define STM32_IC16_DIV DT_PROP(DT_NODELABEL(ic16), ic_div)
775#endif
776
777#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic17), st_stm32n6_ic_clock_mux, okay)
778#define STM32_IC17_ENABLED 1
779#define STM32_IC17_PLL_SRC DT_PROP(DT_NODELABEL(ic17), pll_src)
780#define STM32_IC17_DIV DT_PROP(DT_NODELABEL(ic17), ic_div)
781#endif
782
783#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic18), st_stm32n6_ic_clock_mux, okay)
784#define STM32_IC18_ENABLED 1
785#define STM32_IC18_PLL_SRC DT_PROP(DT_NODELABEL(ic18), pll_src)
786#define STM32_IC18_DIV DT_PROP(DT_NODELABEL(ic18), ic_div)
787#endif
788
789#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic19), st_stm32n6_ic_clock_mux, okay)
790#define STM32_IC19_ENABLED 1
791#define STM32_IC19_PLL_SRC DT_PROP(DT_NODELABEL(ic19), pll_src)
792#define STM32_IC19_DIV DT_PROP(DT_NODELABEL(ic19), ic_div)
793#endif
794
795#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic20), st_stm32n6_ic_clock_mux, okay)
796#define STM32_IC20_ENABLED 1
797#define STM32_IC20_PLL_SRC DT_PROP(DT_NODELABEL(ic20), pll_src)
798#define STM32_IC20_DIV DT_PROP(DT_NODELABEL(ic20), ic_div)
799#endif
800
808
811#define STM32_CLOCK_INFO(clk_index, node_id) \
812 { \
813 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \
814 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) & \
815 GENMASK(STM32_CLOCK_DIV_SHIFT - 1, 0), \
816 .div = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) >> \
817 STM32_CLOCK_DIV_SHIFT, \
818 }
819#define STM32_DT_CLOCKS(node_id) \
820 { \
821 LISTIFY(DT_NUM_CLOCKS(node_id), \
822 STM32_CLOCK_INFO, (,), node_id) \
823 }
824
825#define STM32_DT_INST_CLOCKS(inst) \
826 STM32_DT_CLOCKS(DT_DRV_INST(inst))
827
828#define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) ||
829#define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \
830 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0)
831
832#define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) ||
833#define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \
834 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0)
835
843#define STM32_DT_CLKSEL_REG_GET(clock) \
844 (((clock) >> STM32_DT_CLKSEL_REG_SHIFT) & STM32_DT_CLKSEL_REG_MASK)
845
851#define STM32_DT_CLKSEL_SHIFT_GET(clock) \
852 (((clock) >> STM32_DT_CLKSEL_SHIFT_SHIFT) & STM32_DT_CLKSEL_SHIFT_MASK)
853
859#define STM32_DT_CLKSEL_MASK_GET(clock) \
860 BIT_MASK((((clock) >> STM32_DT_CLKSEL_WIDTH_SHIFT) & STM32_DT_CLKSEL_WIDTH_MASK) + 1)
861
867#define STM32_DT_CLKSEL_VAL_GET(clock) \
868 (((clock) >> STM32_DT_CLKSEL_VAL_SHIFT) & STM32_DT_CLKSEL_VAL_MASK)
869
870#if defined(STM32_HSE_CSS)
879void stm32_hse_css_callback(void);
880#endif
881
882#ifdef CONFIG_SOC_SERIES_STM32WB0X
887typedef void (*lsi_update_cb_t)(uint32_t new_lsi_frequency);
888
900int stm32wb0_register_lsi_update_callback(lsi_update_cb_t cb);
901#endif /* CONFIG_SOC_SERIES_STM32WB0X */
902
903#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */
clock_control.h
Main header file for clock control driver API.
uint32_t
__UINT32_TYPE__ uint32_t
Definition stdint.h:90
stm32_clock.h
STM32_CLOCK_DIV_SHIFT
#define STM32_CLOCK_DIV_SHIFT
Definition stm32_clock.h:27
stm32c0_clock.h
stm32f0_clock.h
stm32f10x_clock.h
stm32f1_clock.h
stm32f3_clock.h
stm32f410_clock.h
stm32f4_clock.h
stm32f7_clock.h
stm32g0_clock.h
stm32g4_clock.h
stm32h5_clock.h
stm32h7_clock.h
stm32h7rs_clock.h
stm32l0_clock.h
stm32l1_clock.h
stm32l4_clock.h
stm32l5_clock.h
stm32mp13_clock.h
stm32mp2_clock.h
stm32n6_clock.h
stm32u0_clock.h
stm32u3_clock.h
stm32u5_clock.h
stm32wb0_clock.h
stm32wb_clock.h
stm32wba_clock.h
stm32wl_clock.h
stm32_pclken
Driver structure definition.
Definition stm32_clock_control.h:803
stm32_pclken::div
uint32_t div
Definition stm32_clock_control.h:805
stm32_pclken::bus
uint32_t bus
Definition stm32_clock_control.h:804
stm32_pclken::enr
uint32_t enr
Definition stm32_clock_control.h:806